This paper examines a conventional method for optimizing the design of CSD multipliers based on parallel Signed-Weight (SW) counter-tree architecture and another novel evolutionary-computation approach to automatically seeking optimal designs of multipliers. The comparisons of experimental results between them indicate that the evolutionary-computation method in most cases is comparable to or outperforms the conventional designs using CSD number representation.
|Number of pages||4|
|Publication status||Published - 2001|
|Event||4th International Conference on ASIC Proceedings - Shanghai, China|
Duration: 2001 Oct 23 → 2001 Oct 25
|Conference||4th International Conference on ASIC Proceedings|
|Period||01/10/23 → 01/10/25|