Abstract
Design of locally computable combinational circuits is a very important issue in the implementation of an ultra-high-speed and compact VLSI chip. We propose a new design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be utilized using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the circuit design algorithm.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
| Publisher | Publ by IEEE |
| Pages | 283-288 |
| Number of pages | 6 |
| ISBN (Print) | 0818633506 |
| Publication status | Published - 1993 Jan 1 |
| Event | Proceedings of the 23rd International Symposium on Multiple-Valued Logic - Sacramento, CA, USA Duration: 1993 May 24 → 1993 May 27 |
Other
| Other | Proceedings of the 23rd International Symposium on Multiple-Valued Logic |
|---|---|
| City | Sacramento, CA, USA |
| Period | 93/5/24 → 93/5/27 |
ASJC Scopus subject areas
- Chemical Health and Safety
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
- Logic