Abstract
To design highly parallel digital circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in digital systems seems to be very attractive because analytical methods can be utilized. For unary operations, the design method of locally computable circuits have been discussed. In this paper, we propose a new design method of highly parallel multiple-valued linear digital circuits for k-ary operations using the concept of identification of input-output graphs by the introduction of multiplicated redundant symbols.
| Original language | English |
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| Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
| Publisher | Publ by IEEE |
| Pages | 223-230 |
| Number of pages | 8 |
| ISBN (Print) | 0818656522 |
| Publication status | Published - 1994 Jan 1 |
| Event | Proceedings of the 24th International Symposium on Multiple-Valued Logic - Boston, MA, USA Duration: 1994 May 25 → 1994 May 27 |
Other
| Other | Proceedings of the 24th International Symposium on Multiple-Valued Logic |
|---|---|
| City | Boston, MA, USA |
| Period | 94/5/25 → 94/5/27 |
ASJC Scopus subject areas
- Chemical Health and Safety
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
- Logic