Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Seongjae Cho; Jung Hoon Lee; Shinichi O'uchi; Kazuhiko Endo; Meishoku Masahara; Byung Gook Park

doi:10.1109/ISDRS.2009.5378143

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Seongjae Cho, Jung Hoon Lee, Shinichi O'uchi, Kazuhiko Endo, Meishoku Masahara, Byung Gook Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	2009 International Semiconductor Device Research Symposium, ISDRS '09
DOIs	https://doi.org/10.1109/ISDRS.2009.5378143
Publication status	Published - 2009
Externally published	Yes
Event	2009 International Semiconductor Device Research Symposium, ISDRS '09 - College Park, MD, United States Duration: 2009 Dec 9 → 2009 Dec 11

Publication series

Name	2009 International Semiconductor Device Research Symposium, ISDRS '09

Other

Other	2009 International Semiconductor Device Research Symposium, ISDRS '09
Country/Territory	United States
City	College Park, MD
Period	09/12/9 → 09/12/11

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISDRS.2009.5378143

Cite this

Cho, S., Lee, J. H., O'uchi, S., Endo, K., Masahara, M., & Park, B. G. (2009). Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL). In 2009 International Semiconductor Device Research Symposium, ISDRS '09 [5378143] (2009 International Semiconductor Device Research Symposium, ISDRS '09). https://doi.org/10.1109/ISDRS.2009.5378143

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL). / Cho, Seongjae; Lee, Jung Hoon; O'uchi, Shinichi et al.
2009 International Semiconductor Device Research Symposium, ISDRS '09. 2009. 5378143 (2009 International Semiconductor Device Research Symposium, ISDRS '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cho, S, Lee, JH, O'uchi, S, Endo, K, Masahara, M & Park, BG 2009, Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL). in 2009 International Semiconductor Device Research Symposium, ISDRS '09., 5378143, 2009 International Semiconductor Device Research Symposium, ISDRS '09, 2009 International Semiconductor Device Research Symposium, ISDRS '09, College Park, MD, United States, 09/12/9. https://doi.org/10.1109/ISDRS.2009.5378143

Cho S, Lee JH, O'uchi S, Endo K, Masahara M, Park BG. Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL). In 2009 International Semiconductor Device Research Symposium, ISDRS '09. 2009. 5378143. (2009 International Semiconductor Device Research Symposium, ISDRS '09). doi: 10.1109/ISDRS.2009.5378143

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author = "Seongjae Cho and Lee, {Jung Hoon} and Shinichi O'uchi and Kazuhiko Endo and Meishoku Masahara and Park, {Byung Gook}",

year = "2009",

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Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Publication series

Other

ASJC Scopus subject areas

Access to Document

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