TY - GEN
T1 - Design of stochastic asymmetric compensation filters for auditory signal processing
AU - Onizawa, Naoya
AU - Koshita, Shunsuke
AU - Sakamoto, Shuichi
AU - Kawamata, Masayuki
AU - Hanyu, Takahiro
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Brainware LSI Project of MEXT and JSPS KAKENHI Grant Number JP16K12494.
Publisher Copyright:
© 2017 IEEE.
PY - 2018/3/7
Y1 - 2018/3/7
N2 - This paper introduces a design of asymmetric compensation filters based on stochastic computation for auditory signal processing. Asymmetric compensation filters are used to model gammachirp filters, which well express the performance of human auditory peripheral mechanism and can be used for hearing assisting devices and noise robust speech recognition systems. Using stochastic computation, the asymmetric compensation filters are simply designed using cascaded IIR filters, thanks to a low-complexity implementation of a multiplication. However, the maximum gain of stochastic filters is limited to 1, causing undesirable filter responses. To address the issue, the proposed flexible gain adjusting (FGA) technique normalizes the gain at each IIR filter in stochastic domain while adjusting the total gain in binary domain. For hardware implementation, stochastic asymmetric compensation filters are designed using TSMC 65 nm CMOS technology and the performance is evaluated with the chip layout generated using a standard cell design flow.
AB - This paper introduces a design of asymmetric compensation filters based on stochastic computation for auditory signal processing. Asymmetric compensation filters are used to model gammachirp filters, which well express the performance of human auditory peripheral mechanism and can be used for hearing assisting devices and noise robust speech recognition systems. Using stochastic computation, the asymmetric compensation filters are simply designed using cascaded IIR filters, thanks to a low-complexity implementation of a multiplication. However, the maximum gain of stochastic filters is limited to 1, causing undesirable filter responses. To address the issue, the proposed flexible gain adjusting (FGA) technique normalizes the gain at each IIR filter in stochastic domain while adjusting the total gain in binary domain. For hardware implementation, stochastic asymmetric compensation filters are designed using TSMC 65 nm CMOS technology and the performance is evaluated with the chip layout generated using a standard cell design flow.
KW - auditory filter
KW - digital circuit implementation
KW - gammachirp filter
KW - IIR filter
KW - stochastic computation
UR - http://www.scopus.com/inward/record.url?scp=85048109857&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048109857&partnerID=8YFLogxK
U2 - 10.1109/GlobalSIP.2017.8309174
DO - 10.1109/GlobalSIP.2017.8309174
M3 - Conference contribution
AN - SCOPUS:85048109857
T3 - 2017 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2017 - Proceedings
SP - 1315
EP - 1319
BT - 2017 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2017 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE Global Conference on Signal and Information Processing, GlobalSIP 2017
Y2 - 14 November 2017 through 16 November 2017
ER -