Design of tamper-resistant registers for multiple-valued cryptographic processors

Yuichi Baba; Naofumi Homma; Atsushi Miyamoto; Takafumi Aoki

doi:10.1109/ISMVL.2010.20

Design of tamper-resistant registers for multiple-valued cryptographic processors

Yuichi Baba, Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.

Original language	English
Title of host publication	ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic
Pages	67-72
Number of pages	6
DOIs	https://doi.org/10.1109/ISMVL.2010.20
Publication status	Published - 2010
Event	40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 - Barcelona, Spain Duration: 2010 May 26 → 2010 May 28

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Conference

Conference	40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010
Country/Territory	Spain
City	Barcelona
Period	10/5/26 → 10/5/28

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10.1109/ISMVL.2010.20

Cite this

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title = "Design of tamper-resistant registers for multiple-valued cryptographic processors",

abstract = "This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.",

author = "Yuichi Baba and Naofumi Homma and Atsushi Miyamoto and Takafumi Aoki",

year = "2010",

doi = "10.1109/ISMVL.2010.20",

language = "English",

isbn = "9780769540245",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

pages = "67--72",

booktitle = "ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic",

note = "40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 ; Conference date: 26-05-2010 Through 28-05-2010",

}

Baba, Y, Homma, N, Miyamoto, A & Aoki, T 2010, Design of tamper-resistant registers for multiple-valued cryptographic processors. in ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic., 5489220, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 67-72, 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010, Barcelona, Spain, 10/5/26. https://doi.org/10.1109/ISMVL.2010.20

Design of tamper-resistant registers for multiple-valued cryptographic processors. / Baba, Yuichi; Homma, Naofumi; Miyamoto, Atsushi et al.
ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic. 2010. p. 67-72 5489220 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of tamper-resistant registers for multiple-valued cryptographic processors

AU - Baba, Yuichi

AU - Homma, Naofumi

AU - Miyamoto, Atsushi

AU - Aoki, Takafumi

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Y1 - 2010

N2 - This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.

AB - This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.

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Design of tamper-resistant registers for multiple-valued cryptographic processors

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