Development of side-channel attack standard evaluation environment

Toshihiro Katashita; Akashi Satoh; Takeshi Sugawara; Naofumi Homma; Takafumi Aoki

doi:10.1109/ECCTD.2009.5275001

Development of side-channel attack standard evaluation environment

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

An experimental FPGA board SASEBO-GII has been developed as a standard platform for advanced research on side-channel attacks and countermeasures. The board is equipped with a new FPGA device, Virtex-5 LX30/50, which provides large logic capacity and dynamic partial reconfiguration. Configuration data can be transferred from a host PC to the FPGA through a USB interface without using a JTAG cable. The USB port can also supply power for operation to the board. Even with these additional functionalities, the size of SASEBO-GII is 1/3 that of the previous board, SASEBO-G. The compactness and circuit design reduce noise that disrupts side-channel analysis. In the paper, the advantages of SASEBO-GII are demonstrated through various AES implementations and CPA experiments.

Original language	English
Title of host publication	ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
Pages	403-408
Number of pages	6
DOIs	https://doi.org/10.1109/ECCTD.2009.5275001
Publication status	Published - 2009
Event	ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program - Antalya, Turkey Duration: 2009 Aug 23 → 2009 Aug 27

Publication series

Name	ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program

Conference

Conference	ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
Country/Territory	Turkey
City	Antalya
Period	09/8/23 → 09/8/27

Access to Document

10.1109/ECCTD.2009.5275001

Cite this

Katashita, T., Satoh, A., Sugawara, T., Homma, N., & Aoki, T. (2009). Development of side-channel attack standard evaluation environment. In ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program (pp. 403-408). Article 5275001 (ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program). https://doi.org/10.1109/ECCTD.2009.5275001

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title = "Development of side-channel attack standard evaluation environment",

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author = "Toshihiro Katashita and Akashi Satoh and Takeshi Sugawara and Naofumi Homma and Takafumi Aoki",

year = "2009",

doi = "10.1109/ECCTD.2009.5275001",

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series = "ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program",

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note = "ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program ; Conference date: 23-08-2009 Through 27-08-2009",

}

Katashita, T, Satoh, A, Sugawara, T, Homma, N & Aoki, T 2009, Development of side-channel attack standard evaluation environment. in ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program., 5275001, ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, pp. 403-408, ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, Antalya, Turkey, 09/8/23. https://doi.org/10.1109/ECCTD.2009.5275001

Development of side-channel attack standard evaluation environment. / Katashita, Toshihiro; Satoh, Akashi; Sugawara, Takeshi et al.
ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program. 2009. p. 403-408 5275001 (ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - An experimental FPGA board SASEBO-GII has been developed as a standard platform for advanced research on side-channel attacks and countermeasures. The board is equipped with a new FPGA device, Virtex-5 LX30/50, which provides large logic capacity and dynamic partial reconfiguration. Configuration data can be transferred from a host PC to the FPGA through a USB interface without using a JTAG cable. The USB port can also supply power for operation to the board. Even with these additional functionalities, the size of SASEBO-GII is 1/3 that of the previous board, SASEBO-G. The compactness and circuit design reduce noise that disrupts side-channel analysis. In the paper, the advantages of SASEBO-GII are demonstrated through various AES implementations and CPA experiments.

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Development of side-channel attack standard evaluation environment

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