Development of SOI pixel process technology

Y. Arai; T. Miyoshi; Y. Unno; T. Tsuboyama; S. Terada; Y. Ikegami; R. Ichimiya; T. Kohriki; K. Tauchi; Y. Ikemoto; Y. Fujita; T. Uchida; K. Hara; H. Miyake; M. Kochiyama; T. Sega; K. Hanagaki; M. Hirose; J. Uchida; Y. Onuki; Y. Horii; H. Yamamoto; T. Tsuru; H. Matsumoto; S. G. Ryu; R. Takashima; A. Takeda; H. Ikeda; D. Kobayashi; T. Wada; H. Nagata; T. Hatsui; T. Kudo; A. Taketani; T. Kameshima; T. Hirono; M. Yabashi; Y. Furukawa; M. Battaglia; P. Denes; C. Vu; D. Contarato; P. Giubilato; T. S. Kim; M. Ohno; K. Fukuda; I. Kurachi; M. Okihara; N. Kuriyama; M. Motoyoshi

doi:10.1016/j.nima.2010.04.081

Development of SOI pixel process technology

Y. Arai, T. Miyoshi, Y. Unno, T. Tsuboyama, S. Terada, Y. Ikegami, R. Ichimiya, T. Kohriki, K. Tauchi, Y. Ikemoto, Y. Fujita, T. Uchida, K. Hara, H. Miyake, M. Kochiyama, T. Sega, K. Hanagaki, M. Hirose, J. Uchida, Y. OnukiY. Horii, H. Yamamoto, T. Tsuru, H. Matsumoto, S. G. Ryu, R. Takashima, A. Takeda, H. Ikeda, D. Kobayashi, T. Wada, H. Nagata, T. Hatsui, T. Kudo, A. Taketani, T. Kameshima, T. Hirono, M. Yabashi, Y. Furukawa, M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, T. S. Kim, M. Ohno, K. Fukuda, I. Kurachi, M. Okihara, N. Kuriyama, M. Motoyoshi

SCI - Physics

Research output: Contribution to journal › Article › peer-review

120 Citations (Scopus)

Abstract

A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.

Original language	English
Pages (from-to)	S31-S36
Journal	Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Volume	636
Issue number	1 SUPPL.
DOIs	https://doi.org/10.1016/j.nima.2010.04.081
Publication status	Published - 2011 Apr 21

Keywords

Particle tracking
Pixel
SOI
X-ray imaging

ASJC Scopus subject areas

Nuclear and High Energy Physics
Instrumentation

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10.1016/j.nima.2010.04.081

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Arai, Y., Miyoshi, T., Unno, Y., Tsuboyama, T., Terada, S., Ikegami, Y., Ichimiya, R., Kohriki, T., Tauchi, K., Ikemoto, Y., Fujita, Y., Uchida, T., Hara, K., Miyake, H., Kochiyama, M., Sega, T., Hanagaki, K., Hirose, M., Uchida, J., ... Motoyoshi, M. (2011). Development of SOI pixel process technology. Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 636(1 SUPPL.), S31-S36. https://doi.org/10.1016/j.nima.2010.04.081

Arai, Y, Miyoshi, T, Unno, Y, Tsuboyama, T, Terada, S, Ikegami, Y, Ichimiya, R, Kohriki, T, Tauchi, K, Ikemoto, Y, Fujita, Y, Uchida, T, Hara, K, Miyake, H, Kochiyama, M, Sega, T, Hanagaki, K, Hirose, M, Uchida, J, Onuki, Y, Horii, Y, Yamamoto, H, Tsuru, T, Matsumoto, H, Ryu, SG, Takashima, R, Takeda, A, Ikeda, H, Kobayashi, D, Wada, T, Nagata, H, Hatsui, T, Kudo, T, Taketani, A, Kameshima, T, Hirono, T, Yabashi, M, Furukawa, Y, Battaglia, M, Denes, P, Vu, C, Contarato, D, Giubilato, P, Kim, TS, Ohno, M, Fukuda, K, Kurachi, I, Okihara, M, Kuriyama, N & Motoyoshi, M 2011, 'Development of SOI pixel process technology', Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 636, no. 1 SUPPL., pp. S31-S36. https://doi.org/10.1016/j.nima.2010.04.081

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title = "Development of SOI pixel process technology",

abstract = "A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.",

keywords = "Particle tracking, Pixel, SOI, X-ray imaging",

author = "Y. Arai and T. Miyoshi and Y. Unno and T. Tsuboyama and S. Terada and Y. Ikegami and R. Ichimiya and T. Kohriki and K. Tauchi and Y. Ikemoto and Y. Fujita and T. Uchida and K. Hara and H. Miyake and M. Kochiyama and T. Sega and K. Hanagaki and M. Hirose and J. Uchida and Y. Onuki and Y. Horii and H. Yamamoto and T. Tsuru and H. Matsumoto and Ryu, {S. G.} and R. Takashima and A. Takeda and H. Ikeda and D. Kobayashi and T. Wada and H. Nagata and T. Hatsui and T. Kudo and A. Taketani and T. Kameshima and T. Hirono and M. Yabashi and Y. Furukawa and M. Battaglia and P. Denes and C. Vu and D. Contarato and P. Giubilato and Kim, {T. S.} and M. Ohno and K. Fukuda and I. Kurachi and M. Okihara and N. Kuriyama and M. Motoyoshi",

note = "Funding Information: This work is supported by KEK Detector Technology Project and JSPS KAKENHI ( 21244040 ). Funding Information: This work is also supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration with Cadence Corporation, Synopsys Corporation, and Mentor Graphics Corporation. ",

year = "2011",

month = apr,

day = "21",

doi = "10.1016/j.nima.2010.04.081",

language = "English",

volume = "636",

pages = "S31--S36",

journal = "Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment",

issn = "0168-9002",

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TY - JOUR

T1 - Development of SOI pixel process technology

AU - Arai, Y.

AU - Miyoshi, T.

AU - Unno, Y.

AU - Tsuboyama, T.

AU - Terada, S.

AU - Ikegami, Y.

AU - Ichimiya, R.

AU - Kohriki, T.

AU - Tauchi, K.

AU - Ikemoto, Y.

AU - Fujita, Y.

AU - Uchida, T.

AU - Hara, K.

AU - Miyake, H.

AU - Kochiyama, M.

AU - Sega, T.

AU - Hanagaki, K.

AU - Hirose, M.

AU - Uchida, J.

AU - Onuki, Y.

AU - Horii, Y.

AU - Yamamoto, H.

AU - Tsuru, T.

AU - Matsumoto, H.

AU - Ryu, S. G.

AU - Takashima, R.

AU - Takeda, A.

AU - Ikeda, H.

AU - Kobayashi, D.

AU - Wada, T.

AU - Nagata, H.

AU - Hatsui, T.

AU - Kudo, T.

AU - Taketani, A.

AU - Kameshima, T.

AU - Hirono, T.

AU - Yabashi, M.

AU - Furukawa, Y.

AU - Battaglia, M.

AU - Denes, P.

AU - Vu, C.

AU - Contarato, D.

AU - Giubilato, P.

AU - Kim, T. S.

AU - Ohno, M.

AU - Fukuda, K.

AU - Kurachi, I.

AU - Okihara, M.

AU - Kuriyama, N.

AU - Motoyoshi, M.

N1 - Funding Information: This work is supported by KEK Detector Technology Project and JSPS KAKENHI ( 21244040 ). Funding Information: This work is also supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration with Cadence Corporation, Synopsys Corporation, and Mentor Graphics Corporation.

PY - 2011/4/21

Y1 - 2011/4/21

N2 - A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.

AB - A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.

KW - Particle tracking

KW - Pixel

KW - SOI

KW - X-ray imaging

UR - http://www.scopus.com/inward/record.url?scp=79955888411&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79955888411&partnerID=8YFLogxK

U2 - 10.1016/j.nima.2010.04.081

DO - 10.1016/j.nima.2010.04.081

M3 - Article

AN - SCOPUS:79955888411

SN - 0168-9002

VL - 636

SP - S31-S36

JO - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

JF - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

IS - 1 SUPPL.

ER -

Development of SOI pixel process technology

Abstract

Keywords

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