A multiple-valued logic-in-memory VLSI with fast reprogrammability is proposed to realize transfer-bottle-neck-free VLSI systems. A basic component, in which a dynamic storage function and a multiple-valued threshold-literal function are merged, can be simply implemented by charge addition and charge storage with a DRAM-cell-based circuit structure. Any logic circuits with multiple-valued inputs and binary outputs can be realized by the combination of the basic components and logic-value conversion. As a typical example, a fully parallel magnitude comparator between three-valued input and stored words is designed by using the proposed logic-in-memory VLSI architecture. Its performance is superior to that of a corresponding binary implementation by using HSPICE simulation under a 0.5 - μm CMOS technology.
|Number of pages||7|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2000|
|Event||ISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic - Portland, OR, USA|
Duration: 2000 May 23 → 2000 May 25