A field-programmable VLSI processor (FPVLSI) is proposed based on a bit-serial pipeline architecture and a mesh network that greatly reduce complexity of a programmable interconnection network. An area-efficient shift-register-based cell is also proposed based on regularity of bit-serial operation. To minimize an inter-cell network, functionality of a programmable switch block is realized only by programming cells. Moreover, direct allocation of a control/data flow graph (CDFG) is introduced to localize data transfer. As a result, an ultra-highly-parallel cellular array is achieved that can efficiently exploit high parallelism of DSP applications. The FPVLSI is designed in a 0.18μm CMOS design rule. Its performance at 700MHz is 4.7 to 9 times higher than that of a conventional FPGA in typical applications under constraints of the same chip area and the same power consumption.