DSP-specific field-programmable VLSI and its CAD environment

Masanori Hariyama, Sho Ogata, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A field-programmable VLSI processor (FPVLSI) is proposed based on a bit-serial pipeline architecture and a mesh network that greatly reduce complexity of a programmable interconnection network. An area-efficient shift-register-based cell is also proposed based on regularity of bit-serial operation. To minimize an inter-cell network, functionality of a programmable switch block is realized only by programming cells. Moreover, direct allocation of a control/data flow graph (CDFG) is introduced to localize data transfer. As a result, an ultra-highly-parallel cellular array is achieved that can efficiently exploit high parallelism of DSP applications. The FPVLSI is designed in a 0.18μm CMOS design rule. Its performance at 700MHz is 4.7 to 9 times higher than that of a conventional FPGA in typical applications under constraints of the same chip area and the same power consumption.

Original languageEnglish
Title of host publication2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages651-654
Number of pages4
DOIs
Publication statusPublished - 2005
Event2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States
Duration: 2005 Aug 72005 Aug 10

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2005
ISSN (Print)1548-3746

Conference

Conference2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Country/TerritoryUnited States
CityCincinnati, OH
Period05/8/705/8/10

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