Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application

Takashi Matsukawa; Kazuhiko Endo; Yongxun Liu; Shin Ichi O'Uchi; Meishoku Masahara; Yuki Ishikawa; Hiromi Yamauchi; Junichi Tsukada; Ken Ichi Ishii; Kunihiro Sakamoto; Eiichi Suzuki

doi:10.1109/ESSDERC.2008.4681753

Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application

Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shin Ichi O'Uchi, Meishoku Masahara, Yuki Ishikawa, Hiromi Yamauchi, Junichi Tsukada, Ken Ichi Ishii, Kunihiro Sakamoto, Eiichi Suzuki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low-Vt CMOS FinFETs representing on-current enhancement and high-Vt CMOS FinFETs reducing stand-by power dramatically, namely multi-Vt CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low-Vt configuration is demonstrated with excellent noise margins at a reduced supply voltage.

Original language	English
Title of host publication	ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference
Publisher	IEEE Computer Society
Pages	282-285
Number of pages	4
ISBN (Print)	9781424423644
DOIs	https://doi.org/10.1109/ESSDERC.2008.4681753
Publication status	Published - 2008
Externally published	Yes
Event	ESSDERC 2008 - 38th European Solid-State Device Research Conference - Edinburgh, Scotland, United Kingdom Duration: 2008 Sept 15 → 2008 Sept 19

Publication series

Name	ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Other

Other	ESSDERC 2008 - 38th European Solid-State Device Research Conference
Country/Territory	United Kingdom
City	Edinburgh, Scotland
Period	08/9/15 → 08/9/19

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSDERC.2008.4681753

Cite this

Matsukawa, T., Endo, K., Liu, Y., O'Uchi, S. I., Masahara, M., Ishikawa, Y., Yamauchi, H., Tsukada, J., Ishii, K. I., Sakamoto, K., & Suzuki, E. (2008). Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application. In ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference (pp. 282-285). [4681753] (ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2008.4681753

Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application. / Matsukawa, Takashi; Endo, Kazuhiko; Liu, Yongxun et al.
ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference. IEEE Computer Society, 2008. p. 282-285 4681753 (ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsukawa, T, Endo, K, Liu, Y, O'Uchi, SI, Masahara, M, Ishikawa, Y, Yamauchi, H, Tsukada, J, Ishii, KI, Sakamoto, K & Suzuki, E 2008, Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application. in ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference., 4681753, ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference, IEEE Computer Society, pp. 282-285, ESSDERC 2008 - 38th European Solid-State Device Research Conference, Edinburgh, Scotland, United Kingdom, 08/9/15. https://doi.org/10.1109/ESSDERC.2008.4681753

Matsukawa T, Endo K, Liu Y, O'Uchi SI, Masahara M, Ishikawa Y et al. Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application. In ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference. IEEE Computer Society. 2008. p. 282-285. 4681753. (ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference). doi: 10.1109/ESSDERC.2008.4681753

Matsukawa, Takashi ; Endo, Kazuhiko ; Liu, Yongxun et al. / Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application. ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference. IEEE Computer Society, 2008. pp. 282-285 (ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference).

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title = "Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application",

abstract = "Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low-Vt CMOS FinFETs representing on-current enhancement and high-Vt CMOS FinFETs reducing stand-by power dramatically, namely multi-Vt CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low-Vt configuration is demonstrated with excellent noise margins at a reduced supply voltage.",

author = "Takashi Matsukawa and Kazuhiko Endo and Yongxun Liu and O'Uchi, {Shin Ichi} and Meishoku Masahara and Yuki Ishikawa and Hiromi Yamauchi and Junichi Tsukada and Ishii, {Ken Ichi} and Kunihiro Sakamoto and Eiichi Suzuki",

note = "Funding Information: This work was supported in part by the Innovation Research Project on Nanoelectronics, Materials and Structures of METI, Japan. ; ESSDERC 2008 - 38th European Solid-State Device Research Conference ; Conference date: 15-09-2008 Through 19-09-2008",

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AU - Matsukawa, Takashi

AU - Endo, Kazuhiko

AU - Liu, Yongxun

AU - O'Uchi, Shin Ichi

AU - Masahara, Meishoku

AU - Ishikawa, Yuki

AU - Yamauchi, Hiromi

AU - Tsukada, Junichi

AU - Ishii, Ken Ichi

AU - Sakamoto, Kunihiro

AU - Suzuki, Eiichi

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AB - Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low-Vt CMOS FinFETs representing on-current enhancement and high-Vt CMOS FinFETs reducing stand-by power dramatically, namely multi-Vt CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low-Vt configuration is demonstrated with excellent noise margins at a reduced supply voltage.

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Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application

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