Abstract
This work presents the first comprehensive evaluation of the manufacturability and reliability of dual WF phase controlled Ni-FUSI/HfSiON CMOS (NMOS: NiSi; PMOS: Ni2Si and Ni31Si12 evaluated) for the 45 nm node. RTP and poly/spacer height were identified as the most critical process control parameters in our flow. We demonstrate that a novel sacrificial SiGe cap addition to the flow (improved poly-Si/spacer height control) opens the RTP1 process window from ∼5°C to ∼20°C for gate lengths down to 45nm, making scalable dual WF CMOS Ni-FUSI manufacturaba. We demonstrate Vt control with σ∼19mV (including wafer to wafer variation, N=1000, 45 nm devices) for NMOS (NiSi), and σ∼21mV for PMOS. TDDB and NBTI reliability evaluation of NiSi and, for the first time, of Ni2Si and Ni31Si12 was done. ∼1V or larger operating voltages (Vop) were extrapolated for a 10 years lifetime. Using a higher backend thermal budget showed no reliability degradation.
Original language | English |
---|---|
Title of host publication | 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers |
Pages | 94-95 |
Number of pages | 2 |
Publication status | Published - 2006 Dec 1 |
Externally published | Yes |
Event | 2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States Duration: 2006 Jun 13 → 2006 Jun 15 |
Other
Other | 2006 Symposium on VLSI Technology, VLSIT |
---|---|
Country/Territory | United States |
City | Honolulu, HI |
Period | 06/6/13 → 06/6/15 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering