Dynamically function-programmable bus architecture for high-throughput intra-chip data transfer

Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu

Research output: Contribution to journalArticlepeer-review


A new common-bus architecture with temporal and spatial parallel access capabilities under wire-resource constraint is proposed to transfer vast quantities of data between modules inside a VLSI chip. Since bus controllers are distributed into modules, the proposed bus architecture can directly transfer data from one module to another without any central bus control unit like a Direct Memory Access (DMA) controller, which enables to reduce communication steps for data transfer between modules. Moreover, when a start address and the number of block data in both source/destination modules are determined at the first step of a data-transfer scheme, no additional address setting for the data transfer is required in the rest of the scheme, which allows us to use all the wire resources as only the "data bus." Therefore, the bus function is dynamically programmed, which results in achieving high throughput of bus communication. For example, in case of a 64-line common bus, it is evaluated that the maximum data throughput in the proposed architecture with dynamic bus-function programming is four times higher than that in the conventional DMA bus architecture with fixed 32-bit-address/32-bit-data buses.

Original languageEnglish
Pages (from-to)1915-1922
Number of pages8
JournalIEICE Transactions on Electronics
Issue number11
Publication statusPublished - 2004 Nov


  • Bus width
  • Common bus
  • Direct data transfer
  • Direct memory access
  • Distributed control


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