Dynamically rule-programmable VLSI processor for fully-parallel inference

T. Hanyu; K. Takeda; T. Higuchi

doi:10.1049/el:19920439

Dynamically rule-programmable VLSI processor for fully-parallel inference

T. Hanyu, K. Takeda, T. Higuchi

Systems & Software Division

Research output: Contribution to journal › Article › peer-review

Abstract

A dynamically rule-programmable fully-parallel inference accelerator VLSI is proposed for real-time rule-based systems with large databases. The direct multiple-valued encoding of each attribute value in rules and the threshold voltage programming of floating-gate MOS devices make a high-performance VLSI possible. The improvement of performance compared with the conventional binary implementation is demonstrated.

Original language	English
Pages (from-to)	695-697
Number of pages	3
Journal	Electronics Letters
Volume	28
Issue number	7
DOIs	https://doi.org/10.1049/el:19920439
Publication status	Published - 1992 Mar

Keywords

Large-scale integration
Parallel processing

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19920439

Cite this

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title = "Dynamically rule-programmable VLSI processor for fully-parallel inference",

abstract = "A dynamically rule-programmable fully-parallel inference accelerator VLSI is proposed for real-time rule-based systems with large databases. The direct multiple-valued encoding of each attribute value in rules and the threshold voltage programming of floating-gate MOS devices make a high-performance VLSI possible. The improvement of performance compared with the conventional binary implementation is demonstrated.",

keywords = "Large-scale integration, Parallel processing",

author = "T. Hanyu and K. Takeda and T. Higuchi",

year = "1992",

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doi = "10.1049/el:19920439",

language = "English",

volume = "28",

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AB - A dynamically rule-programmable fully-parallel inference accelerator VLSI is proposed for real-time rule-based systems with large databases. The direct multiple-valued encoding of each attribute value in rules and the threshold voltage programming of floating-gate MOS devices make a high-performance VLSI possible. The improvement of performance compared with the conventional binary implementation is demonstrated.

KW - Large-scale integration

KW - Parallel processing

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Dynamically rule-programmable VLSI processor for fully-parallel inference

Abstract

Keywords

ASJC Scopus subject areas

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