A dynamically rule-programmable fully-parallel inference accelerator VLSI is proposed for real-time rule-based systems with large databases. The direct multiple-valued encoding of each attribute value in rules and the threshold voltage programming of floating-gate MOS devices make a high-performance VLSI possible. The improvement of performance compared with the conventional binary implementation is demonstrated.
|Number of pages||3|
|Publication status||Published - 1992 Mar|
- Large-scale integration
- Parallel processing
ASJC Scopus subject areas
- Electrical and Electronic Engineering