EFFECT OF SURFACE STATES ON DEVICE AND INTERCONNECT ISOLATION IN GaAs MESFET AND InP MISFET INTEGRATED CIRCUITS.

This paper investigates the surface electrical breakdown and side-gating behavior of GaAs MESFET and InP MISFET integrated circuit structures in order to assess their suitability for highly packed LSI/VLSIs. Using the same layout patterns, a direct comparison of surface breakdown and side-gating behavior is made between both structures formed on semi-insulating substrates passivated with various dielectric films. It is shown that surface states rather than bulk traps primarily limit isolation. High density of surface states on the GaAs surface cause serious premature breakdown and triggers side-gating at a low nominal field intensity of 1-3 kV/cm. On the other hand, InP MISFET integrated circuits are virtually free from these premature breakdown and side-gating effect under normal dark operating condition because of very low surface state density.