Efficient BCH Code Encoding and Decoding Algorithm with Divisor-Distance-Based Polynomial Division for STT-MRAM

Error-correcting codes (ECCs) are important and widely implemented in memories from high-speed SRAM cache to high-volume 3D-NAND. However, from the viewpoint, ECC technology of Spin-transfer torque magnetic random-access memory (STT-MRAM) is not established yet, as the operation speed of STT-MRAM is higher than DRAM/3D-NAND, and its volume is larger than SRAM. Moreover, it is difficult for existing ECCs to guarantee low latency and low hardware complexity while achieving high error correction capabilities. In this work, the time efficiency of both encoding and decoding of Bose-Chaudhuri-Hocquenghem (BCH) codes for STT-MRAM is optimized. A divisor-distance-based (DDB) polynomial division method is proposed to accelerate the polynomial division of BCH encoding and decoding. The DDB division method leverages the characteristics of the divisor polynomial to achieve parallel-processing for multi-bit on the word-line in the same block in a simple manner. And DDB polynomial division method can execute in multiple approaches with different hardware architectures, where the DDB divider with a parallel multiplier (PM) has the lowest hardware complexity. To demonstrate the superiority of the proposed algorithm: The time efficiency of the proposed BCH codes is successfully verified in software, proposed algorithm increases the time efficiency of encoding by more than 10 times, and the decoding increased by about 10%. The hardware implementation of proposed DDB divider is presented for improving the hardware complexity, the PM-type DDB divider architecture eliminates the large memory block of the traditional lookup-table type parallel divider.