Embedded FeRAM macro cell for a smart card microcontroller

Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshima, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Okizaki, Yoichi Miyasaka, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima

Research output: Contribution to journalConference articlepeer-review

13 Citations (Scopus)


This paper describes the circuit technologies and the experimental results for an embedded FeRAM macro cell for a smart card microcontroller. This macro cell employs a 256 byte 2T/2C FeRAM cell array for rewritable nonvolatile memory storage. The macro cell performs read/write operations that are fully synchronous with the microprocessor core, and its write operations are over 1000 times faster than the program operations of a conventional EEPROM macro cell. The macro cell is provided with developed offset sense amplifiers for screening out any weak cells in write endurance. With a small memory cell, as well as a small charge pumping circuit and write circuits, the FeRAM macro cell occupies only half the area of an EEPROM macro. A prototype microcontroller provided with the FeRAM macro cell is fabricated in a standard double metal layer CMOS process with added ferroelectric capacitor process steps.

Original languageEnglish
Pages (from-to)439-442
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1998
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1998 May 111998 May 14


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