Energy-efficient and highly-reliable nonvolatile FPGA using self-terminated power-gating scheme

Daisuke Suzuki; Takahiro Hanyu

doi:10.1109/ISMVL.2016.50

Energy-efficient and highly-reliable nonvolatile FPGA using self-terminated power-gating scheme

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An energy-efficient and highly-reliable nonvolatile FPGA using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular logic cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 64% in comparison with that of a conventional worst-case based approach where the long time write current pulse is used for the reliable write.

Original language	English
Title of host publication	Proceedings - 2016 IEEE 46th International Symposium on Multiple-Valued Logic, ISMVL 2016
Publisher	IEEE Computer Society
Pages	5-10
Number of pages	6
ISBN (Electronic)	9781467394888
DOIs	https://doi.org/10.1109/ISMVL.2016.50
Publication status	Published - 2016 Jul 18
Event	46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016 - Sapporo, Hokkaido, Japan Duration: 2016 May 18 → 2016 May 20

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
Volume	2016-July
ISSN (Print)	0195-623X

Other

Other	46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016
Country/Territory	Japan
City	Sapporo, Hokkaido
Period	16/5/18 → 16/5/20

Keywords

formatting
style
styling

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISMVL.2016.50

Cite this

Suzuki, D., & Hanyu, T. (2016). Energy-efficient and highly-reliable nonvolatile FPGA using self-terminated power-gating scheme. In Proceedings - 2016 IEEE 46th International Symposium on Multiple-Valued Logic, ISMVL 2016 (pp. 5-10). [7515514] (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2016-July). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2016.50

Energy-efficient and highly-reliable nonvolatile FPGA using self-terminated power-gating scheme. / Suzuki, Daisuke; Hanyu, Takahiro.
Proceedings - 2016 IEEE 46th International Symposium on Multiple-Valued Logic, ISMVL 2016. IEEE Computer Society, 2016. p. 5-10 7515514 (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Suzuki, D & Hanyu, T 2016, Energy-efficient and highly-reliable nonvolatile FPGA using self-terminated power-gating scheme. in Proceedings - 2016 IEEE 46th International Symposium on Multiple-Valued Logic, ISMVL 2016., 7515514, Proceedings of The International Symposium on Multiple-Valued Logic, vol. 2016-July, IEEE Computer Society, pp. 5-10, 46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016, Sapporo, Hokkaido, Japan, 16/5/18. https://doi.org/10.1109/ISMVL.2016.50

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Energy-efficient and highly-reliable nonvolatile FPGA using self-terminated power-gating scheme

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

UN SDGs

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