Enhanced Correlation Power Analysis using key screening technique

Toshihiro Katashita; Akashi Satoh; Takeshi Sugawara; Naofumi Homma; Takafumi Aoki

doi:10.1109/ReConFig.2008.16

Enhanced Correlation Power Analysis using key screening technique

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

An enhanced CPA (Correlation Power Analysis) attack which screens key candidates using correlation levels and ranking is proposed in this paper. An AES circuis is implemented on a Xilinx® FPGA on SASEBO (Side-channel Attack Standard Evaluation Board) specifically designed for side-channel attack experiments, and the proposed attack is performed and compared to the standard CPA. As a result, the key screening technique successfully reduces the calculation time for handing 5,000 power traces by 26%. In addition to the accelerated computation, the accuracy of the key estimation is also improved.

Original language	English
Title of host publication	Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008
Pages	403-408
Number of pages	6
DOIs	https://doi.org/10.1109/ReConFig.2008.16
Publication status	Published - 2008 Dec 1
Event	2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008 - Cancun, Mexico Duration: 2008 Dec 3 → 2008 Dec 5

Publication series

Name	Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008

Other

Other	2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008
Country/Territory	Mexico
City	Cancun
Period	08/12/3 → 08/12/5

ASJC Scopus subject areas

Hardware and Architecture
Software

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10.1109/ReConFig.2008.16

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Katashita, T., Satoh, A., Sugawara, T., Homma, N., & Aoki, T. (2008). Enhanced Correlation Power Analysis using key screening technique. In Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008 (pp. 403-408). [4731828] (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008). https://doi.org/10.1109/ReConFig.2008.16

Enhanced Correlation Power Analysis using key screening technique. / Katashita, Toshihiro; Satoh, Akashi; Sugawara, Takeshi et al.

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. 2008. p. 403-408 4731828 (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Katashita, T, Satoh, A, Sugawara, T, Homma, N & Aoki, T 2008, Enhanced Correlation Power Analysis using key screening technique. in Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008., 4731828, Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008, pp. 403-408, 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008, Cancun, Mexico, 08/12/3. https://doi.org/10.1109/ReConFig.2008.16

Katashita T, Satoh A, Sugawara T, Homma N , Aoki T. Enhanced Correlation Power Analysis using key screening technique. In Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. 2008. p. 403-408. 4731828. (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008). doi: 10.1109/ReConFig.2008.16

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title = "Enhanced Correlation Power Analysis using key screening technique",

abstract = "An enhanced CPA (Correlation Power Analysis) attack which screens key candidates using correlation levels and ranking is proposed in this paper. An AES circuis is implemented on a Xilinx{\textregistered} FPGA on SASEBO (Side-channel Attack Standard Evaluation Board) specifically designed for side-channel attack experiments, and the proposed attack is performed and compared to the standard CPA. As a result, the key screening technique successfully reduces the calculation time for handing 5,000 power traces by 26%. In addition to the accelerated computation, the accuracy of the key estimation is also improved.",

author = "Toshihiro Katashita and Akashi Satoh and Takeshi Sugawara and Naofumi Homma and Takafumi Aoki",

year = "2008",

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AU - Satoh, Akashi

AU - Sugawara, Takeshi

AU - Homma, Naofumi

AU - Aoki, Takafumi

PY - 2008/12/1

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N2 - An enhanced CPA (Correlation Power Analysis) attack which screens key candidates using correlation levels and ranking is proposed in this paper. An AES circuis is implemented on a Xilinx® FPGA on SASEBO (Side-channel Attack Standard Evaluation Board) specifically designed for side-channel attack experiments, and the proposed attack is performed and compared to the standard CPA. As a result, the key screening technique successfully reduces the calculation time for handing 5,000 power traces by 26%. In addition to the accelerated computation, the accuracy of the key estimation is also improved.

AB - An enhanced CPA (Correlation Power Analysis) attack which screens key candidates using correlation levels and ranking is proposed in this paper. An AES circuis is implemented on a Xilinx® FPGA on SASEBO (Side-channel Attack Standard Evaluation Board) specifically designed for side-channel attack experiments, and the proposed attack is performed and compared to the standard CPA. As a result, the key screening technique successfully reduces the calculation time for handing 5,000 power traces by 26%. In addition to the accelerated computation, the accuracy of the key estimation is also improved.

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Enhanced Correlation Power Analysis using key screening technique

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