Evaluation of Cu contamination at backside surface of thinned wafer in 3-D integration by transient-capacitance measurement

The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitancetime (C t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (Ct) curves of the MOS capacitor were severely degraded even after initial annealing at 300 °C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO₂ interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.