Evaluation of soft-delay-error effects in content-addressable memory

In recent technology nodes, a timing-error issue due to particle strike into semiconductor materials is getting critical. This paper evaluates a soft-delay-error (SDE) effect due to particle strike for soft-error tolerant content-addressable memories (CAMs). The SDE is that a particle strike into semiconductor materials induces a transient pulse signal, causing a delay variation and a timing error of an integrated circuit. The delay variation is evaluated using a charge-injection model at a transistor level for two different CAMs. One of the CAMs is a traditional 9-transistor-cell based CAM and the other is a magnetic-tunnel-junction (MTJ)/MOS hybrid cell based CAM that operates based on a multiple-valued current-mode logic. These two CAMs are simulated using a SPICE simulator that can handle both transistors and MTJ devices in a 90nm CMOS/100nm MTJ technology. Based on the simulation results, circuit architectures and design parameters are discussed in order to design soft-error tolerant CAMs.