Evolutionary graph generation system with symbolic verification for arithmetic circuit design

N. Homma; T. Aoki; T. Higuchi

doi:10.1049/el:20000704

Evolutionary graph generation system with symbolic verification for arithmetic circuit design

N. Homma, T. Aoki, T. Higuchi

Tohoku University

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within ∼2.2h.

Original language	English
Pages (from-to)	937-939
Number of pages	3
Journal	Electronics Letters
Volume	36
Issue number	11
DOIs	https://doi.org/10.1049/el:20000704
Publication status	Published - 2000 May 25

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abstract = "A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within ∼2.2h.",

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Evolutionary graph generation system with symbolic verification for arithmetic circuit design

Abstract

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