Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform

Y. Morita; T. Mori; K. Fukuda; W. Mizubayashi; S. Migita; T. Matsukawa; K. Endo; S. O'Uchi; Y. Liu; M. Masahara; H. Ota

doi:10.1109/IEDM.2014.7047020

Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform

Y. Morita, T. Mori, K. Fukuda, W. Mizubayashi, S. Migita, T. Matsukawa, K. Endo, S. O'Uchi, Y. Liu, M. Masahara, H. Ota

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

National Institute of Advanced Industrial Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Citations (Scopus)

Abstract

Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 10⁶ and 3 × 10⁴ (with V_D = 0.2 V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.

Original language	English
Title of host publication	2014 IEEE International Electron Devices Meeting, IEDM 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	9.7.1-9.7.4
Edition	February
ISBN (Electronic)	9781479980017
DOIs	https://doi.org/10.1109/IEDM.2014.7047020
Publication status	Published - 2015 Feb 20
Event	2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States Duration: 2014 Dec 15 → 2014 Dec 17

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Number	February
Volume	2015-February
ISSN (Print)	0163-1918

Conference

Conference	2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Country/Territory	United States
City	San Francisco
Period	14/12/15 → 14/12/17

Access to Document

10.1109/IEDM.2014.7047020

Cite this

Morita, Y., Mori, T., Fukuda, K., Mizubayashi, W., Migita, S., Matsukawa, T., Endo, K., O'Uchi, S., Liu, Y., Masahara, M., & Ota, H. (2015). Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform. In 2014 IEEE International Electron Devices Meeting, IEDM 2014 (February ed., pp. 9.7.1-9.7.4). Article 7047020 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2014.7047020

Morita, Y. ; Mori, T. ; Fukuda, K. et al. / Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform. 2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 9.7.1-9.7.4 (Technical Digest - International Electron Devices Meeting, IEDM; February).

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title = "Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform",

abstract = "Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 106 and 3 × 104 (with VD = 0.2 V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.",

author = "Y. Morita and T. Mori and K. Fukuda and W. Mizubayashi and S. Migita and T. Matsukawa and K. Endo and S. O'Uchi and Y. Liu and M. Masahara and H. Ota",

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Morita, Y, Mori, T, Fukuda, K, Mizubayashi, W, Migita, S, Matsukawa, T, Endo, K, O'Uchi, S, Liu, Y, Masahara, M & Ota, H 2015, Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform. in 2014 IEEE International Electron Devices Meeting, IEDM 2014. February edn, 7047020, Technical Digest - International Electron Devices Meeting, IEDM, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 9.7.1-9.7.4, 2014 60th IEEE International Electron Devices Meeting, IEDM 2014, San Francisco, United States, 14/12/15. https://doi.org/10.1109/IEDM.2014.7047020

Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform. / Morita, Y.; Mori, T.; Fukuda, K. et al.
2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 9.7.1-9.7.4 7047020 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Morita, Y.

AU - Mori, T.

AU - Fukuda, K.

AU - Mizubayashi, W.

AU - Migita, S.

AU - Matsukawa, T.

AU - Endo, K.

AU - O'Uchi, S.

AU - Liu, Y.

AU - Masahara, M.

AU - Ota, H.

PY - 2015/2/20

Y1 - 2015/2/20

N2 - Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 106 and 3 × 104 (with VD = 0.2 V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.

AB - Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 106 and 3 × 104 (with VD = 0.2 V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.

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T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 9.7.1-9.7.4

BT - 2014 IEEE International Electron Devices Meeting, IEDM 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 60th IEEE International Electron Devices Meeting, IEDM 2014

Y2 - 15 December 2014 through 17 December 2014

ER -

Morita Y, Mori T, Fukuda K, Mizubayashi W, Migita S, Matsukawa T et al. Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform. In 2014 IEEE International Electron Devices Meeting, IEDM 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 9.7.1-9.7.4. 7047020. (Technical Digest - International Electron Devices Meeting, IEDM; February). doi: 10.1109/IEDM.2014.7047020

Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform

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