TY - JOUR
T1 - Experimental study of floating-gate-type metal-oxide-semiconductor capacitors with nanosize triangular cross-sectional tunnel areas for low operating voltage flash memory application
AU - Liu, Yongxun
AU - Guo, Ruofeng
AU - Kamei, Takahiro
AU - Matsukawa, Takashi
AU - Endo, Kazuhiko
AU - O'Uchi, Shinichi
AU - Tsukada, Junichi
AU - Yamauchi, Hiromi
AU - Ishikawa, Yuki
AU - Hayashida, Tetsuro
AU - Sakamoto, Kunihiro
AU - Ogura, Atsushi
AU - Masahara, Meishoku
PY - 2012/6
Y1 - 2012/6
N2 - The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n + polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO 2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.
AB - The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n + polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO 2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.
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U2 - 10.1143/JJAP.51.06FF01
DO - 10.1143/JJAP.51.06FF01
M3 - Article
AN - SCOPUS:84863317716
SN - 0021-4922
VL - 51
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 6 PART 2
M1 - 06FF01
ER -