Experimental study of tri-gate SOI-FinFET flash memory

Y. X. Liu; T. Kamei; T. Matsukawa; K. Endo; S. O'Uchi; J. Tsukada; H. Yamauchi; Y. Ishikawa; T. Hayashida; K. Sakamoto; A. Ogura; M. Masahara

doi:10.1109/SOI.2012.6404366

Experimental study of tri-gate SOI-FinFET flash memory

Y. X. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1-3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4-7]. In this paper, we report the experimental results of the FG type SOI-FinFET flash memories including gate structure dependent of V_t variability and SCE immunity. We also report the FinFET flash memories with split-gate and with an improved inter-poly dielectric (IPD) layer.

Original language	English
Title of host publication	2012 IEEE International SOI Conference, SOI 2012
DOIs	https://doi.org/10.1109/SOI.2012.6404366
Publication status	Published - 2012
Event	2012 IEEE International SOI Conference, SOI 2012 - Napa, CA, United States Duration: 2012 Oct 1 → 2012 Oct 4

Publication series

Name	Proceedings - IEEE International SOI Conference
ISSN (Print)	1078-621X

Conference

Conference	2012 IEEE International SOI Conference, SOI 2012
Country/Territory	United States
City	Napa, CA
Period	12/10/1 → 12/10/4

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Liu, Y. X., Kamei, T., Matsukawa, T., Endo, K., O'Uchi, S., Tsukada, J., Yamauchi, H., Ishikawa, Y., Hayashida, T., Sakamoto, K., Ogura, A., & Masahara, M. (2012). Experimental study of tri-gate SOI-FinFET flash memory. In 2012 IEEE International SOI Conference, SOI 2012 Article 6404366 (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2012.6404366

@inproceedings{bb6e78e695ab49eb922accce6a6d1b44,

title = "Experimental study of tri-gate SOI-FinFET flash memory",

abstract = "It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1-3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4-7]. In this paper, we report the experimental results of the FG type SOI-FinFET flash memories including gate structure dependent of Vt variability and SCE immunity. We also report the FinFET flash memories with split-gate and with an improved inter-poly dielectric (IPD) layer.",

author = "Liu, {Y. X.} and T. Kamei and T. Matsukawa and K. Endo and S. O'Uchi and J. Tsukada and H. Yamauchi and Y. Ishikawa and T. Hayashida and K. Sakamoto and A. Ogura and M. Masahara",

year = "2012",

doi = "10.1109/SOI.2012.6404366",

language = "English",

isbn = "9781467326919",

series = "Proceedings - IEEE International SOI Conference",

booktitle = "2012 IEEE International SOI Conference, SOI 2012",

note = "2012 IEEE International SOI Conference, SOI 2012 ; Conference date: 01-10-2012 Through 04-10-2012",

}

Liu, YX, Kamei, T, Matsukawa, T, Endo, K, O'Uchi, S, Tsukada, J, Yamauchi, H, Ishikawa, Y, Hayashida, T, Sakamoto, K, Ogura, A & Masahara, M 2012, Experimental study of tri-gate SOI-FinFET flash memory. in 2012 IEEE International SOI Conference, SOI 2012., 6404366, Proceedings - IEEE International SOI Conference, 2012 IEEE International SOI Conference, SOI 2012, Napa, CA, United States, 12/10/1. https://doi.org/10.1109/SOI.2012.6404366

TY - GEN

T1 - Experimental study of tri-gate SOI-FinFET flash memory

AU - Liu, Y. X.

AU - Kamei, T.

AU - Matsukawa, T.

AU - Endo, K.

AU - O'Uchi, S.

AU - Tsukada, J.

AU - Yamauchi, H.

AU - Ishikawa, Y.

AU - Hayashida, T.

AU - Sakamoto, K.

AU - Ogura, A.

AU - Masahara, M.

PY - 2012

Y1 - 2012

N2 - It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1-3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4-7]. In this paper, we report the experimental results of the FG type SOI-FinFET flash memories including gate structure dependent of Vt variability and SCE immunity. We also report the FinFET flash memories with split-gate and with an improved inter-poly dielectric (IPD) layer.

AB - It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1-3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4-7]. In this paper, we report the experimental results of the FG type SOI-FinFET flash memories including gate structure dependent of Vt variability and SCE immunity. We also report the FinFET flash memories with split-gate and with an improved inter-poly dielectric (IPD) layer.

UR - http://www.scopus.com/inward/record.url?scp=84873560519&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84873560519&partnerID=8YFLogxK

U2 - 10.1109/SOI.2012.6404366

DO - 10.1109/SOI.2012.6404366

M3 - Conference contribution

AN - SCOPUS:84873560519

SN - 9781467326919

T3 - Proceedings - IEEE International SOI Conference

BT - 2012 IEEE International SOI Conference, SOI 2012

T2 - 2012 IEEE International SOI Conference, SOI 2012

Y2 - 1 October 2012 through 4 October 2012

ER -

Experimental study of tri-gate SOI-FinFET flash memory

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