TY - JOUR
T1 - Fabrication method of sub-100nm metal-oxide-semiconductor field-effect transistor with thick gate oxide
AU - Singh, Vipul
AU - Inokawa, Hiroshi
AU - Endoh, Tetsuo
AU - Satoh, Hiroaki
PY - 2010/12
Y1 - 2010/12
N2 - Based on the standard large-scale integrated circuit (LSI) process, sub-100nm gate metal-oxide-semiconductor field-effect transistor (MOSFET) with thick gate oxide was fabricated. This was realized only by the modification of layout design, and no customization of the fabrication process was necessary. This unique designing technique is of great use in obtaining low-input-leakage MOSFET by advanced LSI process for highperformance analog applications.
AB - Based on the standard large-scale integrated circuit (LSI) process, sub-100nm gate metal-oxide-semiconductor field-effect transistor (MOSFET) with thick gate oxide was fabricated. This was realized only by the modification of layout design, and no customization of the fabrication process was necessary. This unique designing technique is of great use in obtaining low-input-leakage MOSFET by advanced LSI process for highperformance analog applications.
UR - http://www.scopus.com/inward/record.url?scp=79551649146&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79551649146&partnerID=8YFLogxK
U2 - 10.1143/JJAP.49.128002
DO - 10.1143/JJAP.49.128002
M3 - Article
AN - SCOPUS:79551649146
SN - 0021-4922
VL - 49
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 12
M1 - 128002
ER -