Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

Daisuke Suzuki; Masanori Natsui; Shoji Ikeda; Haruhiro Hasegawa; Katsuya Miura; Jun Hayakawa; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

72 Citations (Scopus)

Abstract

Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14μm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.

Original language	English
Title of host publication	2009 Symposium on VLSI Circuits
Pages	80-81
Number of pages	2
Publication status	Published - 2009
Event	2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2009 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

Cite this

Suzuki, D., Natsui, M., Ikeda, S., Hasegawa, H., Miura, K., Hayakawa, J., Endoh, T., Ohno, H., & Hanyu, T. (2009). Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array. In 2009 Symposium on VLSI Circuits (pp. 80-81). Article 5205282 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{cebdec217a7f4cd7b5f453a820608971,

title = "Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array",

abstract = "Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14μm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.",

author = "Daisuke Suzuki and Masanori Natsui and Shoji Ikeda and Haruhiro Hasegawa and Katsuya Miura and Jun Hayakawa and Tetsuo Endoh and Hideo Ohno and Takahiro Hanyu",

year = "2009",

language = "English",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "80--81",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

}

Suzuki, D, Natsui, M , Ikeda, S, Hasegawa, H, Miura, K, Hayakawa, J, Endoh, T , Ohno, H & Hanyu, T 2009, Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array. in 2009 Symposium on VLSI Circuits., 5205282, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 80-81, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array. / Suzuki, Daisuke; Natsui, Masanori ; Ikeda, Shoji et al.
2009 Symposium on VLSI Circuits. 2009. p. 80-81 5205282 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

AU - Suzuki, Daisuke

AU - Natsui, Masanori

AU - Ikeda, Shoji

AU - Hasegawa, Haruhiro

AU - Miura, Katsuya

AU - Hayakawa, Jun

AU - Endoh, Tetsuo

AU - Ohno, Hideo

AU - Hanyu, Takahiro

PY - 2009

Y1 - 2009

N2 - Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14μm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.

AB - Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14μm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.

UR - http://www.scopus.com/inward/record.url?scp=70449359801&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70449359801&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:70449359801

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 80

EP - 81

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

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