Fabrication of silicon pillar with 25nm half pitch using new multiple double patterning technique

For the higher-density cells of next-generation semiconductor memories, many recent studies have focused on the vertical cell structure technology, which includes various performance merits such as small cell size, high drivability, and suitability for cell-stacked-type arrays. The authors developed a new method to fabricate 25nm half pitch dense Si pillars that would be applicable to the fabrication of vertical cell devices. Using the proposed multiple double patterning techniques, 23.6nm diameter, 114nm height Si cylindrical pillars with a half pitch of 25nm were fabricated. We confirmed the uniformity in a 300mm wafer at 30 points, and its 3- was only 1.7 nm. Moreover, we examined the presence of pillar collapse at arbitrarily selected chip dies for confirmation. Surprisingly, there was no pillar collapse within any of the inspected areas. From these verifications, we conclude that our proposed fabrication technique for slim Si pillars is now available.