FASTBUS TDC SYSTEM.

M. Ikeno; S. Inaba; T. Kondo; S. Odaka; H. Sagawa; F. Suekane; Y. Watase; M. Miyazawa

FASTBUS TDC SYSTEM.

M. Ikeno, S. Inaba, T. Kondo, S. Odaka, H. Sagawa, F. Suekane, Y. Watase, M. Miyazawa

Research Center for Neutrino Science (RCNS)

High Energy Accelerator Research Organization, Tsukuba

Research output: Contribution to journal › Article › peer-review

Abstract

A new time digitizing system has been developed for the large scale drift chambers used in the colliding beam experiments at TRISTAN. The system is based on 64-channel single-hit time-to-amplitude converter (TAC) modules with analog multiplexers and a scan ADC (SADC). Up to 1536 TAC channels in a FASTBUS crate are scanned and AD converted by a SADC in the same crate. Hardware data processings such as pedestal and slope corrections (Ax plus B), address conversions, sparse data scanning, and test hit-pattern loading are available.

Original language	English
Journal	IEEE Transactions on Nuclear Science
Volume	NS-33
Issue number	1
Publication status	Published - 1985 Feb

Cite this

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author = "M. Ikeno and S. Inaba and T. Kondo and S. Odaka and H. Sagawa and F. Suekane and Y. Watase and M. Miyazawa",

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AU - Ikeno, M.

AU - Inaba, S.

AU - Kondo, T.

AU - Odaka, S.

AU - Sagawa, H.

AU - Suekane, F.

AU - Watase, Y.

AU - Miyazawa, M.

PY - 1985/2

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AB - A new time digitizing system has been developed for the large scale drift chambers used in the colliding beam experiments at TRISTAN. The system is based on 64-channel single-hit time-to-amplitude converter (TAC) modules with analog multiplexers and a scan ADC (SADC). Up to 1536 TAC channels in a FASTBUS crate are scanned and AD converted by a SADC in the same crate. Hardware data processings such as pedestal and slope corrections (Ax plus B), address conversions, sparse data scanning, and test hit-pattern loading are available.

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FASTBUS TDC SYSTEM.

Abstract

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