FeRAM device and circuit technologies fully compatible with advanced CMOS

H. Toyoshima; S. Kobayashi; J. Yamada; T. Miwa; H. Koike; H. Takeuchi; H. Mori; N. Kasai; Y. Maejima; A. Seike; N. Tanabe; T. Tatsumi; H. Hada

FeRAM device and circuit technologies fully compatible with advanced CMOS

H. Toyoshima, S. Kobayashi, J. Yamada, T. Miwa, H. Koike, H. Takeuchi, H. Mori, N. Kasai, Y. Maejima, A. Seike, N. Tanabe, T. Tatsumi, H. Hada

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced logic CMOS is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-μm 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-μm ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.

Original language	English
Pages (from-to)	171-178
Number of pages	8
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 2001 Jan 1
Externally published	Yes
Event	IEEE 2001 Custom Integrated Circuits Conference - San Diego, CA, United States Duration: 2001 May 6 → 2001 May 9

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "FeRAM device and circuit technologies fully compatible with advanced CMOS",

abstract = "Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced logic CMOS is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-μm 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-μm ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.",

author = "H. Toyoshima and S. Kobayashi and J. Yamada and T. Miwa and H. Koike and H. Takeuchi and H. Mori and N. Kasai and Y. Maejima and A. Seike and N. Tanabe and T. Tatsumi and H. Hada",

year = "2001",

month = jan,

day = "1",

language = "English",

pages = "171--178",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE 2001 Custom Integrated Circuits Conference ; Conference date: 06-05-2001 Through 09-05-2001",

}

TY - JOUR

T1 - FeRAM device and circuit technologies fully compatible with advanced CMOS

AU - Toyoshima, H.

AU - Kobayashi, S.

AU - Yamada, J.

AU - Miwa, T.

AU - Koike, H.

AU - Takeuchi, H.

AU - Mori, H.

AU - Kasai, N.

AU - Maejima, Y.

AU - Seike, A.

AU - Tanabe, N.

AU - Tatsumi, T.

AU - Hada, H.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced logic CMOS is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-μm 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-μm ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.

AB - Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced logic CMOS is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-μm 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-μm ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.

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M3 - Conference article

AN - SCOPUS:0034820419

SN - 0886-5930

SP - 171

EP - 178

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - IEEE 2001 Custom Integrated Circuits Conference

Y2 - 6 May 2001 through 9 May 2001

ER -

FeRAM device and circuit technologies fully compatible with advanced CMOS

Abstract

ASJC Scopus subject areas

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