A functional pass-gate based on ferroelectrics for fine grain pipelined very large scale integration (VLSI) computation is discussed. A potential application of the VLSI computation is shown using a 250 MHz pipelined multiplier with 16 pipeline stages. The pipeline pitch is found by the delay of a single functional pass gate. The timing diagram in which the basic behavior of the proposed ferroelectric based serial adder is also demonstrated.
|Digest of Technical Papers - IEEE International Solid-State Circuits Conference
|Published - 2002
|2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 3 → 2002 Feb 7