Field-programmable VLSI based on a bit-serial fine-grain architecture

Masanori Hariyama, Weisheng Chong, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


This paper presents a novel architecture to solve two problems of existing FPGAs: the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.

Original languageEnglish
Pages (from-to)1897-1902
Number of pages6
JournalIEICE Transactions on Electronics
Issue number11
Publication statusPublished - 2004 Nov


  • Bit-serial architecture
  • FPGA
  • Reconfigurable architecture

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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