Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance

Tetsuro Hayashida; Kazuhiko Endo; Yongxun Liu; Shin Ichi O'Uchi; Takashi Matsukawa; Wataru Mizubayashi; Shinji Migita; Yukinori Morita; Hiroyuki Ota; Hiroki Hashiguchi; Daisuke Kosemura; Takahiro Kamei; Junichi Tsukada; Yuki Ishikawa; Hiromi Yamauchi; Atsushi Ogura; Meishoku Masahara

doi:10.1109/TED.2011.2181385

Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance

Tetsuro Hayashida, Kazuhiko Endo, Yongxun Liu, Shin Ichi O'Uchi, Takashi Matsukawa, Wataru Mizubayashi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Hiroki Hashiguchi, Daisuke Kosemura, Takahiro Kamei, Junichi Tsukada, Yuki Ishikawa, Hiromi Yamauchi, Atsushi Ogura, Meishoku Masahara

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

We compared the electrical characteristics, including mobility and on -state current I _on, of n ⁺-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights H _fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length L _g decreases, I _on for devices with tall fins becomes worse, probably due to a high parasitic resistance R _p. Furthermore, V _th variation increased with increasing H _fin due to rough etching of the fin sidewall. Process technologies for reducing R _p and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

Original language	English
Article number	6148269
Pages (from-to)	647-653
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	59
Issue number	3
DOIs	https://doi.org/10.1109/TED.2011.2181385
Publication status	Published - 2012 Mar

Keywords

fin height
FinFET
mobility
parasitic resistance titanium nitride (TiN)

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10.1109/TED.2011.2181385

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Hayashida, T., Endo, K., Liu, Y., O'Uchi, S. I., Matsukawa, T., Mizubayashi, W., Migita, S., Morita, Y., Ota, H., Hashiguchi, H., Kosemura, D., Kamei, T., Tsukada, J., Ishikawa, Y., Yamauchi, H., Ogura, A., & Masahara, M. (2012). Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance. IEEE Transactions on Electron Devices, 59(3), 647-653. Article 6148269. https://doi.org/10.1109/TED.2011.2181385

@article{73d10816db9f40429d3f63312318598c,

title = "Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance",

abstract = "We compared the electrical characteristics, including mobility and on -state current I on, of n +-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights H fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length L g decreases, I on for devices with tall fins becomes worse, probably due to a high parasitic resistance R p. Furthermore, V th variation increased with increasing H fin due to rough etching of the fin sidewall. Process technologies for reducing R p and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.",

keywords = "fin height, FinFET, mobility, parasitic resistance titanium nitride (TiN)",

author = "Tetsuro Hayashida and Kazuhiko Endo and Yongxun Liu and O'Uchi, {Shin Ichi} and Takashi Matsukawa and Wataru Mizubayashi and Shinji Migita and Yukinori Morita and Hiroyuki Ota and Hiroki Hashiguchi and Daisuke Kosemura and Takahiro Kamei and Junichi Tsukada and Yuki Ishikawa and Hiromi Yamauchi and Atsushi Ogura and Meishoku Masahara",

note = "Funding Information: Manuscript received September 6, 2011; revised November 18, 2011; accepted December 14, 2011. Date of current version February 23, 2012. This work was supported in part by the Development of Nanoelectronics Devices Technology of the New Energy and Industrial Technology Development Organization, Japan. The review of this paper was arranged by Editor A. Schenk.",

year = "2012",

month = mar,

doi = "10.1109/TED.2011.2181385",

language = "English",

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pages = "647--653",

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Hayashida, T, Endo, K, Liu, Y, O'Uchi, SI, Matsukawa, T, Mizubayashi, W, Migita, S, Morita, Y, Ota, H, Hashiguchi, H, Kosemura, D, Kamei, T, Tsukada, J, Ishikawa, Y, Yamauchi, H, Ogura, A & Masahara, M 2012, 'Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance', IEEE Transactions on Electron Devices, vol. 59, no. 3, 6148269, pp. 647-653. https://doi.org/10.1109/TED.2011.2181385

TY - JOUR

T1 - Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance

AU - Hayashida, Tetsuro

AU - Endo, Kazuhiko

AU - Liu, Yongxun

AU - O'Uchi, Shin Ichi

AU - Matsukawa, Takashi

AU - Mizubayashi, Wataru

AU - Migita, Shinji

AU - Morita, Yukinori

AU - Ota, Hiroyuki

AU - Hashiguchi, Hiroki

AU - Kosemura, Daisuke

AU - Kamei, Takahiro

AU - Tsukada, Junichi

AU - Ishikawa, Yuki

AU - Yamauchi, Hiromi

AU - Ogura, Atsushi

AU - Masahara, Meishoku

N1 - Funding Information: Manuscript received September 6, 2011; revised November 18, 2011; accepted December 14, 2011. Date of current version February 23, 2012. This work was supported in part by the Development of Nanoelectronics Devices Technology of the New Energy and Industrial Technology Development Organization, Japan. The review of this paper was arranged by Editor A. Schenk.

PY - 2012/3

Y1 - 2012/3

N2 - We compared the electrical characteristics, including mobility and on -state current I on, of n +-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights H fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length L g decreases, I on for devices with tall fins becomes worse, probably due to a high parasitic resistance R p. Furthermore, V th variation increased with increasing H fin due to rough etching of the fin sidewall. Process technologies for reducing R p and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

AB - We compared the electrical characteristics, including mobility and on -state current I on, of n +-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights H fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length L g decreases, I on for devices with tall fins becomes worse, probably due to a high parasitic resistance R p. Furthermore, V th variation increased with increasing H fin due to rough etching of the fin sidewall. Process technologies for reducing R p and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

KW - fin height

KW - FinFET

KW - mobility

KW - parasitic resistance titanium nitride (TiN)

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JF - IEEE Transactions on Electron Devices

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ER -

Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance

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Keywords

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