Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction

Magdalena Sihotang; Shoun Matsunaga; Takahiro Hanyu

doi:10.1109/NEWCAS.2012.6329062

Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction

Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu

RIEC - Computing System Platforms Division

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Data-transfer localization is a key technique to solve communication bottleneck between memory and logic modules in realizing high-speed VLSI systems, while it is difficult to use power-gating technique because volatile storage functions are distributed in a CMOS logic-circuit plane, which causes large power dissipation. In this paper, we utilize nonvolatile logic-in-memory (NV-LIM) architecture, where nonvolatile storage functions are distributed over a logic-circuit plane, to solve the above issues. As a typical example of the NV-LIM circuit, we apply it to motion-vector extraction. By the use of fine-grained power-gating technique, total power dissipation of the proposed hardware can be reduced to 60% in comparison with that of a conventional CMOS-only-based hardware.

Original language	English
Title of host publication	2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
Pages	485-488
Number of pages	4
DOIs	https://doi.org/10.1109/NEWCAS.2012.6329062
Publication status	Published - 2012
Event	2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 - Montreal, QC, Canada Duration: 2012 Jun 17 → 2012 Jun 20

Publication series

Name	2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012

Conference

Conference	2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
Country/Territory	Canada
City	Montreal, QC
Period	12/6/17 → 12/6/20

Keywords

fine-grained pipelining
image compression
logic-in-memory architecture
MRAM
spintronics
sum-of-absolute-difference operation

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10.1109/NEWCAS.2012.6329062

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Sihotang, M., Matsunaga, S., & Hanyu, T. (2012). Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. In 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 (pp. 485-488). Article 6329062 (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012). https://doi.org/10.1109/NEWCAS.2012.6329062

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abstract = "Data-transfer localization is a key technique to solve communication bottleneck between memory and logic modules in realizing high-speed VLSI systems, while it is difficult to use power-gating technique because volatile storage functions are distributed in a CMOS logic-circuit plane, which causes large power dissipation. In this paper, we utilize nonvolatile logic-in-memory (NV-LIM) architecture, where nonvolatile storage functions are distributed over a logic-circuit plane, to solve the above issues. As a typical example of the NV-LIM circuit, we apply it to motion-vector extraction. By the use of fine-grained power-gating technique, total power dissipation of the proposed hardware can be reduced to 60% in comparison with that of a conventional CMOS-only-based hardware.",

keywords = "fine-grained pipelining, image compression, logic-in-memory architecture, MRAM, spintronics, sum-of-absolute-difference operation",

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Sihotang, M, Matsunaga, S & Hanyu, T 2012, Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. in 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012., 6329062, 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012, pp. 485-488, 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012, Montreal, QC, Canada, 12/6/17. https://doi.org/10.1109/NEWCAS.2012.6329062

Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. / Sihotang, Magdalena; Matsunaga, Shoun; Hanyu, Takahiro.
2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. 2012. p. 485-488 6329062 (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Sihotang M, Matsunaga S, Hanyu T. Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. In 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. 2012. p. 485-488. 6329062. (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012). doi: 10.1109/NEWCAS.2012.6329062

Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction

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