FinFET flash memory technology

Y. X. Liu; T. Kamei; T. Matsukawa; K. Endo; S. O'uchi; J. Tsukada; H. Yamauchi; Y. Ishikawa; T. Hayashida; K. Sakamoto; A. Ogura; M. Masahara

doi:10.1149/1.3700894

FinFET flash memory technology

Y. X. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

The crystal-Si and poly-Si fin-channel flash memories with a thin n ⁺-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (V_t) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that V_t variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BV _DS) was higher than 3.2 V even the gate length (L_g) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.

Original language	English
Title of host publication	Dielectrics for Nanosystems 5
Subtitle of host publication	Materials Science, Processing, Reliability, and Manufacturing -and- Tutorials in Nanotechnology: More than Moore - Beyond CMOS Emerging Materials and Devices
Publisher	Electrochemical Society Inc.
Pages	289-310
Number of pages	22
Edition	3
ISBN (Electronic)	9781607683131
ISBN (Print)	9781566779555
DOIs	https://doi.org/10.1149/1.3700894
Publication status	Published - 2012
Event	5th International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 221st ECS Meeting - Seattle, WA, United States Duration: 2012 May 6 → 2012 May 10

Publication series

Name	ECS Transactions
Number	3
Volume	45
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	5th International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 221st ECS Meeting
Country/Territory	United States
City	Seattle, WA
Period	12/5/6 → 12/5/10

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10.1149/1.3700894

Cite this

Liu, Y. X., Kamei, T., Matsukawa, T., Endo, K., O'uchi, S., Tsukada, J., Yamauchi, H., Ishikawa, Y., Hayashida, T., Sakamoto, K., Ogura, A., & Masahara, M. (2012). FinFET flash memory technology. In Dielectrics for Nanosystems 5: Materials Science, Processing, Reliability, and Manufacturing -and- Tutorials in Nanotechnology: More than Moore - Beyond CMOS Emerging Materials and Devices (3 ed., pp. 289-310). (ECS Transactions; Vol. 45, No. 3). Electrochemical Society Inc.. https://doi.org/10.1149/1.3700894

@inproceedings{a3e4a6eb345342e3923e6f3fd38dc716,

title = "FinFET flash memory technology",

abstract = "The crystal-Si and poly-Si fin-channel flash memories with a thin n +-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BV DS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.",

author = "Liu, {Y. X.} and T. Kamei and T. Matsukawa and K. Endo and S. O'uchi and J. Tsukada and H. Yamauchi and Y. Ishikawa and T. Hayashida and K. Sakamoto and A. Ogura and M. Masahara",

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doi = "10.1149/1.3700894",

language = "English",

isbn = "9781566779555",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "3",

pages = "289--310",

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edition = "3",

note = "5th International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 221st ECS Meeting ; Conference date: 06-05-2012 Through 10-05-2012",

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Liu, YX, Kamei, T, Matsukawa, T, Endo, K, O'uchi, S, Tsukada, J, Yamauchi, H, Ishikawa, Y, Hayashida, T, Sakamoto, K, Ogura, A & Masahara, M 2012, FinFET flash memory technology. in Dielectrics for Nanosystems 5: Materials Science, Processing, Reliability, and Manufacturing -and- Tutorials in Nanotechnology: More than Moore - Beyond CMOS Emerging Materials and Devices. 3 edn, ECS Transactions, no. 3, vol. 45, Electrochemical Society Inc., pp. 289-310, 5th International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 221st ECS Meeting, Seattle, WA, United States, 12/5/6. https://doi.org/10.1149/1.3700894

FinFET flash memory technology. / Liu, Y. X.; Kamei, T.; Matsukawa, T. et al.
Dielectrics for Nanosystems 5: Materials Science, Processing, Reliability, and Manufacturing -and- Tutorials in Nanotechnology: More than Moore - Beyond CMOS Emerging Materials and Devices. 3. ed. Electrochemical Society Inc., 2012. p. 289-310 (ECS Transactions; Vol. 45, No. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FinFET flash memory technology

AU - Liu, Y. X.

AU - Kamei, T.

AU - Matsukawa, T.

AU - Endo, K.

AU - O'uchi, S.

AU - Tsukada, J.

AU - Yamauchi, H.

AU - Ishikawa, Y.

AU - Hayashida, T.

AU - Sakamoto, K.

AU - Ogura, A.

AU - Masahara, M.

PY - 2012

Y1 - 2012

N2 - The crystal-Si and poly-Si fin-channel flash memories with a thin n +-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BV DS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.

AB - The crystal-Si and poly-Si fin-channel flash memories with a thin n +-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BV DS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.

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U2 - 10.1149/1.3700894

DO - 10.1149/1.3700894

M3 - Conference contribution

AN - SCOPUS:84869077899

SN - 9781566779555

T3 - ECS Transactions

SP - 289

EP - 310

BT - Dielectrics for Nanosystems 5

PB - Electrochemical Society Inc.

T2 - 5th International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufacturing - 221st ECS Meeting

Y2 - 6 May 2012 through 10 May 2012

ER -

Liu YX, Kamei T, Matsukawa T, Endo K, O'uchi S, Tsukada J et al. FinFET flash memory technology. In Dielectrics for Nanosystems 5: Materials Science, Processing, Reliability, and Manufacturing -and- Tutorials in Nanotechnology: More than Moore - Beyond CMOS Emerging Materials and Devices. 3 ed. Electrochemical Society Inc. 2012. p. 289-310. (ECS Transactions; 3). doi: 10.1149/1.3700894

FinFET flash memory technology

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