First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

S. W. Chang; J. H. Li; M. K. Huang; Y. C. Huang; S. T. Huang; H. C. Wang; Y. J. Huang; J. Y. Wang; L. W. Yu; Y. F. Huang; F. K. Hsueh; P. J. Sung; C. T. Wu; W. C.Y. Ma; K. H. Kao; Y. J. Lee; C. L. Lin; R. W. Chuang; K. P. Huang; S. Samukawa; Y. Li; W. H. Lee; T. Y. Chu; T. S. Chao; G. W. Huang; W. F. Wu; J. Y. Li; J. M. Shieh; W. K. Yeh; Y. H. Wang; D. D. Lu; C. J. Wang; N. C. Lin; C. J. Su; S. H. Lo; H. F. Huang

doi:10.1109/IEDM19573.2019.8993525

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

S. W. Chang, J. H. Li, M. K. Huang, Y. C. Huang, S. T. Huang, H. C. Wang, Y. J. Huang, J. Y. Wang, L. W. Yu, Y. F. Huang, F. K. Hsueh, P. J. Sung, C. T. Wu, W. C.Y. Ma, K. H. Kao, Y. J. Lee, C. L. Lin, R. W. Chuang, K. P. Huang, S. SamukawaY. Li, W. H. Lee, T. Y. Chu, T. S. Chao, G. W. Huang, W. F. Wu, J. Y. Li, J. M. Shieh, W. K. Yeh, Y. H. Wang, D. D. Lu, C. J. Wang, N. C. Lin, C. J. Su, S. H. Lo, H. F. Huang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

28 Citations (Scopus)

Abstract

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

Original language	English
Title of host publication	2019 IEEE International Electron Devices Meeting, IEDM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728140315
DOIs	https://doi.org/10.1109/IEDM19573.2019.8993525
Publication status	Published - 2019 Dec
Externally published	Yes
Event	65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: 2019 Dec 7 → 2019 Dec 11

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2019-December
ISSN (Print)	0163-1918

Conference

Conference	65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country/Territory	United States
City	San Francisco
Period	19/12/7 → 19/12/11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Access to Document

10.1109/IEDM19573.2019.8993525

Cite this

Chang, S. W., Li, J. H., Huang, M. K., Huang, Y. C., Huang, S. T., Wang, H. C., Huang, Y. J., Wang, J. Y., Yu, L. W., Huang, Y. F., Hsueh, F. K., Sung, P. J., Wu, C. T., Ma, W. C. Y., Kao, K. H., Lee, Y. J., Lin, C. L., Chuang, R. W., Huang, K. P., ... Huang, H. F. (2019). First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications. In 2019 IEEE International Electron Devices Meeting, IEDM 2019 [8993525] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19573.2019.8993525

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications. / Chang, S. W.; Li, J. H.; Huang, M. K. et al.
2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993525 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chang, SW, Li, JH, Huang, MK, Huang, YC, Huang, ST, Wang, HC, Huang, YJ, Wang, JY, Yu, LW, Huang, YF, Hsueh, FK, Sung, PJ, Wu, CT, Ma, WCY, Kao, KH, Lee, YJ, Lin, CL, Chuang, RW, Huang, KP, Samukawa, S, Li, Y, Lee, WH, Chu, TY, Chao, TS, Huang, GW, Wu, WF, Li, JY, Shieh, JM, Yeh, WK, Wang, YH, Lu, DD, Wang, CJ, Lin, NC, Su, CJ, Lo, SH & Huang, HF 2019, First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993525, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 19/12/7. https://doi.org/10.1109/IEDM19573.2019.8993525

Chang SW, Li JH, Huang MK, Huang YC, Huang ST, Wang HC et al. First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications. In 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8993525. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM19573.2019.8993525

@inproceedings{40cdeb55d20e404a8600f577b565a942,

title = "First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications",

abstract = "For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.",

author = "Chang, {S. W.} and Li, {J. H.} and Huang, {M. K.} and Huang, {Y. C.} and Huang, {S. T.} and Wang, {H. C.} and Huang, {Y. J.} and Wang, {J. Y.} and Yu, {L. W.} and Huang, {Y. F.} and Hsueh, {F. K.} and Sung, {P. J.} and Wu, {C. T.} and Ma, {W. C.Y.} and Kao, {K. H.} and Lee, {Y. J.} and Lin, {C. L.} and Chuang, {R. W.} and Huang, {K. P.} and S. Samukawa and Y. Li and Lee, {W. H.} and Chu, {T. Y.} and Chao, {T. S.} and Huang, {G. W.} and Wu, {W. F.} and Li, {J. Y.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.} and Lu, {D. D.} and Wang, {C. J.} and Lin, {N. C.} and Su, {C. J.} and Lo, {S. H.} and Huang, {H. F.}",

note = "Funding Information: This work was performed by the Taiwan Semiconductor Research Institute facilities and supported by the Ministry of Science and Technology, Taiwan under grant numbers 107-2636-E-006-004, 108-2636-E-006-004, 108-3017-F-009-003, 107-2628-E-492-001-MY3, and 108-2634-F-006-008, and Hitachi High-Technologies Corp. Japan. REFERENCES [1] H. Mertens et al., IEDM Tech. Dig., 2017, pp.828-831. [2] N. Loubet et al., Proc. Symp. VLSI Tech., 2017, pp. 230-231. [3] J. Ryckaert et al., Proc. Symp. VLSI Tech., 2018, pp. 141-142. [4] J.-P. Colinge et al., Nature Nanotechnology, 2010, pp.225-229. [5] M. V. Dunga et al., Proc. Symp. VLSI Tech., 2007, pp. 60-61. [6] Sentaurus Device, Synopsys Inc., 2018. 2017. [7] Wen et al., Proc. IITC, 2016, pp. 34-36. [8] C.-C. Yang, et al., IEDM Tech. Dig., 2015, pp.206-209. [9] P. Batude, et al., Proc. Symp. VLSI Tech., 2015, pp.48-49. [10] V. Deshpande, et al., IEDM Tech. Dig., 2015, pp.209-212. [11] V. Deshpande et al., Proc. Symp. VLSI Tech., 2017, pp.74-75. Publisher Copyright: {\textcopyright} 2019 IEEE.; 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 ; Conference date: 07-12-2019 Through 11-12-2019",

year = "2019",

month = dec,

doi = "10.1109/IEDM19573.2019.8993525",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",

}

TY - GEN

T1 - First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

AU - Chang, S. W.

AU - Li, J. H.

AU - Huang, M. K.

AU - Huang, Y. C.

AU - Huang, S. T.

AU - Wang, H. C.

AU - Huang, Y. J.

AU - Wang, J. Y.

AU - Yu, L. W.

AU - Huang, Y. F.

AU - Hsueh, F. K.

AU - Sung, P. J.

AU - Wu, C. T.

AU - Ma, W. C.Y.

AU - Kao, K. H.

AU - Lee, Y. J.

AU - Lin, C. L.

AU - Chuang, R. W.

AU - Huang, K. P.

AU - Samukawa, S.

AU - Li, Y.

AU - Lee, W. H.

AU - Chu, T. Y.

AU - Chao, T. S.

AU - Huang, G. W.

AU - Wu, W. F.

AU - Li, J. Y.

AU - Shieh, J. M.

AU - Yeh, W. K.

AU - Wang, Y. H.

AU - Lu, D. D.

AU - Wang, C. J.

AU - Lin, N. C.

AU - Su, C. J.

AU - Lo, S. H.

AU - Huang, H. F.

N1 - Funding Information: This work was performed by the Taiwan Semiconductor Research Institute facilities and supported by the Ministry of Science and Technology, Taiwan under grant numbers 107-2636-E-006-004, 108-2636-E-006-004, 108-3017-F-009-003, 107-2628-E-492-001-MY3, and 108-2634-F-006-008, and Hitachi High-Technologies Corp. Japan. REFERENCES [1] H. Mertens et al., IEDM Tech. Dig., 2017, pp.828-831. [2] N. Loubet et al., Proc. Symp. VLSI Tech., 2017, pp. 230-231. [3] J. Ryckaert et al., Proc. Symp. VLSI Tech., 2018, pp. 141-142. [4] J.-P. Colinge et al., Nature Nanotechnology, 2010, pp.225-229. [5] M. V. Dunga et al., Proc. Symp. VLSI Tech., 2007, pp. 60-61. [6] Sentaurus Device, Synopsys Inc., 2018. 2017. [7] Wen et al., Proc. IITC, 2016, pp. 34-36. [8] C.-C. Yang, et al., IEDM Tech. Dig., 2015, pp.206-209. [9] P. Batude, et al., Proc. Symp. VLSI Tech., 2015, pp.48-49. [10] V. Deshpande, et al., IEDM Tech. Dig., 2015, pp.209-212. [11] V. Deshpande et al., Proc. Symp. VLSI Tech., 2017, pp.74-75. Publisher Copyright: © 2019 IEEE.

PY - 2019/12

Y1 - 2019/12

N2 - For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

AB - For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

UR - http://www.scopus.com/inward/record.url?scp=85081065128&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85081065128&partnerID=8YFLogxK

U2 - 10.1109/IEDM19573.2019.8993525

DO - 10.1109/IEDM19573.2019.8993525

M3 - Conference contribution

AN - SCOPUS:85081065128

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 65th Annual IEEE International Electron Devices Meeting, IEDM 2019

Y2 - 7 December 2019 through 11 December 2019

ER -

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this