TY - JOUR
T1 - Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration
AU - Fukushima, Takafumi
AU - Alam, Arsalan
AU - Hanna, Amir
AU - Jangam, Siva Chandra
AU - Bajwa, Adeel Ahmad
AU - Iyer, Subramanian S.
N1 - Funding Information:
Manuscript received April 30, 2018; revised August 26, 2018; accepted September 10, 2018. Date of publication September 20, 2018; date of current version October 10, 2018. This work was supported in part by the Defense Advanced Research Projects Agency through ONR under Grant N00014-16-1-263, in part by NBMC, and in part by the Air Force Research Laboratory under Agreement FA8650-13-2-7311. Recommended for publication by Associate Editor P. P. Conway upon evaluation of reviewers’ comments. (Corresponding author: Takafumi Fukushima.) T. Fukushima is with the Department of Mechanical Systems Engineering, Tohoku University, Sendai 980-8579, Japan (e-mail: fukushima@lbc.mech. tohoku.ac.jp).
Publisher Copyright:
© 2011-2012 IEEE.
PY - 2018/10
Y1 - 2018/10
N2 - A technological platform is established for scalable flexible hybrid electronics based on a novel fan-out wafer-level packaging (FOWLP) methodology. Small dielets are embedded in flexible substrates we call FlexTrate. These dielets can be interconnected through high-density wirings formed in wafer-level processing. We demonstrate homogeneous integration of 625 (25 by 25) 1-mm2 Si dielets and heterogeneous integration of GaAs and Si dielets with various thicknesses in a biocompatible polydimethylsiloxane (PDMS). In this paper, 8-μm-pitch die-to-die interconnections are successfully implemented over a stress buffer layer formed on the PDMS. In addition, coplanarity between the PDMS and embedded dielets, die shift concerned in typical die-first FOWLP, and the bendability of the resulting FlexTrate are characterized.
AB - A technological platform is established for scalable flexible hybrid electronics based on a novel fan-out wafer-level packaging (FOWLP) methodology. Small dielets are embedded in flexible substrates we call FlexTrate. These dielets can be interconnected through high-density wirings formed in wafer-level processing. We demonstrate homogeneous integration of 625 (25 by 25) 1-mm2 Si dielets and heterogeneous integration of GaAs and Si dielets with various thicknesses in a biocompatible polydimethylsiloxane (PDMS). In this paper, 8-μm-pitch die-to-die interconnections are successfully implemented over a stress buffer layer formed on the PDMS. In addition, coplanarity between the PDMS and embedded dielets, die shift concerned in typical die-first FOWLP, and the bendability of the resulting FlexTrate are characterized.
KW - Fan-out wafer-level packaging (FOWLP)
KW - flexible hybrid electronics (FHE)
KW - flexible substrate
KW - heterogeneous integration
KW - high-density interconnect
KW - polydimethylsiloxane (PDMS)
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U2 - 10.1109/TCPMT.2018.2871603
DO - 10.1109/TCPMT.2018.2871603
M3 - Article
AN - SCOPUS:85053632172
SN - 2156-3950
VL - 8
SP - 1738
EP - 1746
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
IS - 10
M1 - 8469036
ER -