Four-terminal double-gate logic for LSTP applications below 32-nm technology node

S. O'uchi; Y. X. Liu; M. Masahara; T. Tsutsumi; K. Endo; T. Nakagawa; M. Hioki; T. Sekigawa; H. Koike; E. Suzuki

Four-terminal double-gate logic for LSTP applications below 32-nm technology node

S. O'uchi, Y. X. Liu, M. Masahara, T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

National Institute of Advanced Industrial Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A logic system consisting of four-terminal double-gate MSOFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node, A scaling strategy for the 4T-DG logic is also provided.

Original language	English
Title of host publication	2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06
Publication status	Published - 2006
Event	Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference - Padova, Italy Duration: 2006 May 24 → 2006 May 26

Publication series

Name	2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Conference

Conference	Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference
Country/Territory	Italy
City	Padova
Period	06/5/24 → 06/5/26

Keywords

4T-DGFET
Fin
TCAD mixed mode and LSTP
Threshold voltage control technique

Cite this

O'uchi, S., Liu, Y. X., Masahara, M., Tsutsumi, T., Endo, K., Nakagawa, T., Hioki, M., Sekigawa, T., Koike, H., & Suzuki, E. (2006). Four-terminal double-gate logic for LSTP applications below 32-nm technology node. In 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06 Article 1669388 (2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06).

@inproceedings{9a58395d05054d44b47cc8330f653059,

title = "Four-terminal double-gate logic for LSTP applications below 32-nm technology node",

abstract = "A logic system consisting of four-terminal double-gate MSOFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node, A scaling strategy for the 4T-DG logic is also provided.",

keywords = "4T-DGFET, Fin, TCAD mixed mode and LSTP, Threshold voltage control technique",

author = "S. O'uchi and Liu, {Y. X.} and M. Masahara and T. Tsutsumi and K. Endo and T. Nakagawa and M. Hioki and T. Sekigawa and H. Koike and E. Suzuki",

year = "2006",

language = "English",

isbn = "1424400988",

series = "2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06",

booktitle = "2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06",

note = "Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference ; Conference date: 24-05-2006 Through 26-05-2006",

}

O'uchi, S, Liu, YX, Masahara, M, Tsutsumi, T, Endo, K, Nakagawa, T, Hioki, M, Sekigawa, T, Koike, H & Suzuki, E 2006, Four-terminal double-gate logic for LSTP applications below 32-nm technology node. in 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06., 1669388, 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06, Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference, Padova, Italy, 06/5/24.

Four-terminal double-gate logic for LSTP applications below 32-nm technology node. / O'uchi, S.; Liu, Y. X.; Masahara, M. et al.
2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06. 2006. 1669388 (2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Four-terminal double-gate logic for LSTP applications below 32-nm technology node

AU - O'uchi, S.

AU - Liu, Y. X.

AU - Masahara, M.

AU - Tsutsumi, T.

AU - Endo, K.

AU - Nakagawa, T.

AU - Hioki, M.

AU - Sekigawa, T.

AU - Koike, H.

AU - Suzuki, E.

PY - 2006

Y1 - 2006

N2 - A logic system consisting of four-terminal double-gate MSOFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node, A scaling strategy for the 4T-DG logic is also provided.

AB - A logic system consisting of four-terminal double-gate MSOFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node, A scaling strategy for the 4T-DG logic is also provided.

KW - 4T-DGFET

KW - Fin

KW - TCAD mixed mode and LSTP

KW - Threshold voltage control technique

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M3 - Conference contribution

AN - SCOPUS:42749107482

SN - 1424400988

SN - 9781424400980

T3 - 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

BT - 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

T2 - Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference

Y2 - 24 May 2006 through 26 May 2006

ER -

Four-terminal double-gate logic for LSTP applications below 32-nm technology node

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Keywords

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