Four-terminal FinFET device technology

M. Masahara; K. Endo; Y. X. Liu; S. O'uchi; T. Matsukawa; R. Surdeanu; L. Witters; G. Doombos; V. H. Nguyen; G. Van Den Bosch; C. Vrancken; M. Jurczak; S. Biesemans; E. Suzuki

doi:10.1109/ICICDT.2007.4299542

Four-terminal FinFET device technology

M. Masahara, K. Endo, Y. X. Liu, S. O'uchi, T. Matsukawa, R. Surdeanu, L. Witters, G. Doombos, V. H. Nguyen, G. Van Den Bosch, C. Vrancken, M. Jurczak, S. Biesemans, E. Suzuki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal- FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a promising potential to overcome this issue thanks to a post-fabrication flexible V^th controllability in addition to their superior SCE immunity. This paper presents novel 4T-FinFET device technology based on experimental demonstrations. Newly-developed DG separation processes for the 4T-FinFETs, successful fabrication of the optimum 4T-FinFET with asymmetric gate oxides, and dynamic power management demonstration using 4T-FinFET are presented.

Original language	English
Title of host publication	Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages	55-58
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2007.4299542
Publication status	Published - 2007 Dec 1
Externally published	Yes
Event	2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States Duration: 2007 May 30 → 2007 Jun 1

Publication series

Name	Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other	2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin, TX
Period	07/5/30 → 07/6/1

Keywords

4T-FinFET
Asymmetric gate oxide thickness
Double gate separation
Dynamic power management
Flexible V control

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICICDT.2007.4299542

Cite this

Masahara, M., Endo, K., Liu, Y. X., O'uchi, S., Matsukawa, T., Surdeanu, R., Witters, L., Doombos, G., Nguyen, V. H., Van Den Bosch, G., Vrancken, C., Jurczak, M., Biesemans, S., & Suzuki, E. (2007). Four-terminal FinFET device technology. In Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 55-58). [4299542] (Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/ICICDT.2007.4299542

Four-terminal FinFET device technology. / Masahara, M.; Endo, K.; Liu, Y. X. et al.

Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2007. p. 55-58 4299542 (Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Masahara, M, Endo, K, Liu, YX, O'uchi, S, Matsukawa, T, Surdeanu, R, Witters, L, Doombos, G, Nguyen, VH, Van Den Bosch, G, Vrancken, C, Jurczak, M, Biesemans, S & Suzuki, E 2007, Four-terminal FinFET device technology. in Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT., 4299542, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, pp. 55-58, 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 07/5/30. https://doi.org/10.1109/ICICDT.2007.4299542

Masahara M, Endo K, Liu YX, O'uchi S, Matsukawa T, Surdeanu R et al. Four-terminal FinFET device technology. In Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2007. p. 55-58. 4299542. (Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). doi: 10.1109/ICICDT.2007.4299542

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AU - Witters, L.

AU - Doombos, G.

AU - Nguyen, V. H.

AU - Van Den Bosch, G.

AU - Vrancken, C.

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AB - One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal- FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a promising potential to overcome this issue thanks to a post-fabrication flexible Vth controllability in addition to their superior SCE immunity. This paper presents novel 4T-FinFET device technology based on experimental demonstrations. Newly-developed DG separation processes for the 4T-FinFETs, successful fabrication of the optimum 4T-FinFET with asymmetric gate oxides, and dynamic power management demonstration using 4T-FinFET are presented.

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Four-terminal FinFET device technology

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Keywords

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