Four-terminal FinFETs fabricated using an etch-back gate separation

Kazuhiko Endo; Yuki Ishikawa; Yongxun Liu; Kenichi Ishii; Takashi Matsukawa; Shin Ichi O'uchi; Meishoku Masahara; Etsuro Sugimata; Jyunichi Tsukada; Hiromi Yamauchi; Eiichi Suzuki

doi:10.1109/TNANO.2007.891830

Four-terminal FinFETs fabricated using an etch-back gate separation

Kazuhiko Endo, Yuki Ishikawa, Yongxun Liu, Kenichi Ishii, Takashi Matsukawa, Shin Ichi O'uchi, Meishoku Masahara, Etsuro Sugimata, Jyunichi Tsukada, Hiromi Yamauchi, Eiichi Suzuki

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

National Institute of Advanced Industrial Science and Technology

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient V_th controllability. The effective V_th controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode.

Original language	English
Pages (from-to)	201-204
Number of pages	4
Journal	IEEE Transactions on Nanotechnology
Volume	6
Issue number	2
DOIs	https://doi.org/10.1109/TNANO.2007.891830
Publication status	Published - 2007 Mar

Keywords

Etch-back
FinFET
Four-terminal
Gate-separation
V control

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10.1109/TNANO.2007.891830

Cite this

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title = "Four-terminal FinFETs fabricated using an etch-back gate separation",

abstract = "A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode.",

keywords = "Etch-back, FinFET, Four-terminal, Gate-separation, V control",

author = "Kazuhiko Endo and Yuki Ishikawa and Yongxun Liu and Kenichi Ishii and Takashi Matsukawa and O'uchi, {Shin Ichi} and Meishoku Masahara and Etsuro Sugimata and Jyunichi Tsukada and Hiromi Yamauchi and Eiichi Suzuki",

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doi = "10.1109/TNANO.2007.891830",

language = "English",

volume = "6",

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T1 - Four-terminal FinFETs fabricated using an etch-back gate separation

AU - Endo, Kazuhiko

AU - Ishikawa, Yuki

AU - Liu, Yongxun

AU - Ishii, Kenichi

AU - Matsukawa, Takashi

AU - O'uchi, Shin Ichi

AU - Masahara, Meishoku

AU - Sugimata, Etsuro

AU - Tsukada, Jyunichi

AU - Yamauchi, Hiromi

AU - Suzuki, Eiichi

PY - 2007/3

Y1 - 2007/3

N2 - A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode.

AB - A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode.

KW - Etch-back

KW - FinFET

KW - Four-terminal

KW - Gate-separation

KW - V control

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JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

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Four-terminal FinFETs fabricated using an etch-back gate separation

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Keywords

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