FPGA implementation of a vehicle detection algorithm using three-dimensional information

Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a vehicle detection algorithm using 3-dimensional(3-D) information and its FPGA implementation. For high-speed acquisition of 3-D information, feature-based stereo matching is employed to reduce search area. Our algorithm consists of some tasks with high degree of column-level parallelism. Based on the parallelism, we propose area-efficient VLSI architecture with local data transfer between memory modules and processing elements. Images are equally divided into blocks with some columns, and a block is allocated to a PE. Each PE performs the processing in parallel. The proposed architecture is implemented on FPGA (Altera Stratix EP1S40F1020C7). For specifications of image size 640 x 480, 100 frames/sec, and operating frequency 100MHz, only 11,000 logic elements (< 30%) are required for 30PEs.

Original languageEnglish
Title of host publicationIPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM
DOIs
Publication statusPublished - 2008
EventIPDPS 2008 - 22nd IEEE International Parallel and Distributed Processing Symposium - Miami, FL, United States
Duration: 2008 Apr 142008 Apr 18

Publication series

NameIPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

Other

OtherIPDPS 2008 - 22nd IEEE International Parallel and Distributed Processing Symposium
Country/TerritoryUnited States
CityMiami, FL
Period08/4/1408/4/18

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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