Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging

Murugesan Murugesan; Takafumi Fukushima; Kiyoharu Mori; Ai Nakamura; Yisang Lee; Makoto Motoyoshi; J. C. Bea; Shigeru Watariguchi; Mitsumasa Koyanagi

doi:10.1109/ECTC.2019.00164

Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging

Murugesan Murugesan, Takafumi Fukushima, Kiyoharu Mori, Ai Nakamura, Yisang Lee, Makoto Motoyoshi, J. C. Bea, Shigeru Watariguchi, Mitsumasa Koyanagi

ENG - Mechanical Systems Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Citations (Scopus)

Abstract

Si interposer with 10 μm-width, 100 μm-deep through-silicon via (TSV) has been fabricated using electroless (EL) Ni as barrier and seed layers, and characterized for their electrical resistance. The chemistry of electroless-Ni plating bath was meticulously adjusted for the conformal formation of Ni along the TSV side wall. From the resistance value of 36 ΩW per TSV obtained from the Kelvin measurement of these Cu-TSV chain showed that the electroless Ni layer well acts as a good seed layer for completely filling the high aspect ratio TSVs by Cu-electroplating.

Original language	English
Title of host publication	Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1047-1051
Number of pages	5
ISBN (Electronic)	9781728114989
DOIs	https://doi.org/10.1109/ECTC.2019.00164
Publication status	Published - 2019 May
Event	69th IEEE Electronic Components and Technology Conference, ECTC 2019 - Las Vegas, United States Duration: 2019 May 28 → 2019 May 31

Publication series

Name	Proceedings - Electronic Components and Technology Conference
Volume	2019-May
ISSN (Print)	0569-5503

Conference

Conference	69th IEEE Electronic Components and Technology Conference, ECTC 2019
Country/Territory	United States
City	Las Vegas
Period	19/5/28 → 19/5/31

Keywords

Barrier/seed laer
Cu-diffusion
Cu-TSV
Electroless Ni
Si interposer

Access to Document

10.1109/ECTC.2019.00164

Cite this

Murugesan, M., Fukushima, T., Mori, K., Nakamura, A., Lee, Y., Motoyoshi, M., Bea, J. C., Watariguchi, S., & Koyanagi, M. (2019). Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging. In Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019 (pp. 1047-1051). Article 8811299 (Proceedings - Electronic Components and Technology Conference; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2019.00164

Murugesan, Murugesan ; Fukushima, Takafumi ; Mori, Kiyoharu et al. / Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging. Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 1047-1051 (Proceedings - Electronic Components and Technology Conference).

@inproceedings{6b7a19c81bd944e1a0acdb8e5f14389b,

title = "Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging",

abstract = "Si interposer with 10 μm-width, 100 μm-deep through-silicon via (TSV) has been fabricated using electroless (EL) Ni as barrier and seed layers, and characterized for their electrical resistance. The chemistry of electroless-Ni plating bath was meticulously adjusted for the conformal formation of Ni along the TSV side wall. From the resistance value of 36 ΩW per TSV obtained from the Kelvin measurement of these Cu-TSV chain showed that the electroless Ni layer well acts as a good seed layer for completely filling the high aspect ratio TSVs by Cu-electroplating.",

keywords = "Barrier/seed laer, Cu-diffusion, Cu-TSV, Electroless Ni, Si interposer",

author = "Murugesan Murugesan and Takafumi Fukushima and Kiyoharu Mori and Ai Nakamura and Yisang Lee and Makoto Motoyoshi and Bea, {J. C.} and Shigeru Watariguchi and Mitsumasa Koyanagi",

note = "Funding Information: Part of this work was performed at the Junichi Nishizawa Research Center and Micro/Nano-machining research and education Center (MNC) at Tohoku University, Japan. Publisher Copyright: {\textcopyright} 2019 IEEE.; 69th IEEE Electronic Components and Technology Conference, ECTC 2019 ; Conference date: 28-05-2019 Through 31-05-2019",

year = "2019",

month = may,

doi = "10.1109/ECTC.2019.00164",

language = "English",

series = "Proceedings - Electronic Components and Technology Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1047--1051",

booktitle = "Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019",

address = "United States",

}

Murugesan, M, Fukushima, T, Mori, K, Nakamura, A, Lee, Y, Motoyoshi, M, Bea, JC, Watariguchi, S & Koyanagi, M 2019, Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging. in Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019., 8811299, Proceedings - Electronic Components and Technology Conference, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., pp. 1047-1051, 69th IEEE Electronic Components and Technology Conference, ECTC 2019, Las Vegas, United States, 19/5/28. https://doi.org/10.1109/ECTC.2019.00164

Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging. / Murugesan, Murugesan; Fukushima, Takafumi; Mori, Kiyoharu et al.
Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 1047-1051 8811299 (Proceedings - Electronic Components and Technology Conference; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging

AU - Murugesan, Murugesan

AU - Fukushima, Takafumi

AU - Mori, Kiyoharu

AU - Nakamura, Ai

AU - Lee, Yisang

AU - Motoyoshi, Makoto

AU - Bea, J. C.

AU - Watariguchi, Shigeru

AU - Koyanagi, Mitsumasa

N1 - Funding Information: Part of this work was performed at the Junichi Nishizawa Research Center and Micro/Nano-machining research and education Center (MNC) at Tohoku University, Japan. Publisher Copyright: © 2019 IEEE.

PY - 2019/5

Y1 - 2019/5

N2 - Si interposer with 10 μm-width, 100 μm-deep through-silicon via (TSV) has been fabricated using electroless (EL) Ni as barrier and seed layers, and characterized for their electrical resistance. The chemistry of electroless-Ni plating bath was meticulously adjusted for the conformal formation of Ni along the TSV side wall. From the resistance value of 36 ΩW per TSV obtained from the Kelvin measurement of these Cu-TSV chain showed that the electroless Ni layer well acts as a good seed layer for completely filling the high aspect ratio TSVs by Cu-electroplating.

AB - Si interposer with 10 μm-width, 100 μm-deep through-silicon via (TSV) has been fabricated using electroless (EL) Ni as barrier and seed layers, and characterized for their electrical resistance. The chemistry of electroless-Ni plating bath was meticulously adjusted for the conformal formation of Ni along the TSV side wall. From the resistance value of 36 ΩW per TSV obtained from the Kelvin measurement of these Cu-TSV chain showed that the electroless Ni layer well acts as a good seed layer for completely filling the high aspect ratio TSVs by Cu-electroplating.

KW - Barrier/seed laer

KW - Cu-diffusion

KW - Cu-TSV

KW - Electroless Ni

KW - Si interposer

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DO - 10.1109/ECTC.2019.00164

M3 - Conference contribution

AN - SCOPUS:85072284992

T3 - Proceedings - Electronic Components and Technology Conference

SP - 1047

EP - 1051

BT - Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 69th IEEE Electronic Components and Technology Conference, ECTC 2019

Y2 - 28 May 2019 through 31 May 2019

ER -

Murugesan M, Fukushima T, Mori K, Nakamura A, Lee Y, Motoyoshi M et al. Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging. In Proceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 1047-1051. 8811299. (Proceedings - Electronic Components and Technology Conference). doi: 10.1109/ECTC.2019.00164

Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging

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Keywords

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