Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

T. Amazawa; E. Yamamoto; K. Sakuma; Y. Ito; K. Kamoshida; K. Ikeda; K. Saito; H. Ishii; S. Kato; S. Yagi; K. Hiraoka; T. Ueki; T. Takeda; Y. Arita

Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

T. Amazawa, E. Yamamoto, K. Sakuma, Y. Ito, K. Kamoshida, K. Ikeda, K. Saito, H. Ishii, S. Kato, S. Yagi, K. Hiraoka, T. Ueki, T. Takeda, Y. Arita

Research Institute of Electrical Communication (RIEC)

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 μ m, equal pitch, four-level interconnection.

Original language	English
Pages (from-to)	473-476
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1995 Dec 1
Event	Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA Duration: 1995 Dec 10 → 1995 Dec 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

Amazawa, T., Yamamoto, E., Sakuma, K., Ito, Y., Kamoshida, K., Ikeda, K., Saito, K., Ishii, H., Kato, S., Yagi, S., Hiraoka, K., Ueki, T., Takeda, T., & Arita, Y. (1995). Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs. Technical Digest - International Electron Devices Meeting, 473-476.

Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs. / Amazawa, T.; Yamamoto, E.; Sakuma, K. et al.
In: Technical Digest - International Electron Devices Meeting, 01.12.1995, p. 473-476.

Research output: Contribution to journal › Conference article › peer-review

Amazawa, T, Yamamoto, E, Sakuma, K, Ito, Y, Kamoshida, K, Ikeda, K, Saito, K, Ishii, H, Kato, S, Yagi, S, Hiraoka, K, Ueki, T, Takeda, T & Arita, Y 1995, 'Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs', Technical Digest - International Electron Devices Meeting, pp. 473-476.

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abstract = "The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 μ m, equal pitch, four-level interconnection.",

author = "T. Amazawa and E. Yamamoto and K. Sakuma and Y. Ito and K. Kamoshida and K. Ikeda and K. Saito and H. Ishii and S. Kato and S. Yagi and K. Hiraoka and T. Ueki and T. Takeda and Y. Arita",

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T1 - Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

AU - Amazawa, T.

AU - Yamamoto, E.

AU - Sakuma, K.

AU - Ito, Y.

AU - Kamoshida, K.

AU - Ikeda, K.

AU - Saito, K.

AU - Ishii, H.

AU - Kato, S.

AU - Yagi, S.

AU - Hiraoka, K.

AU - Ueki, T.

AU - Takeda, T.

AU - Arita, Y.

PY - 1995/12/1

Y1 - 1995/12/1

N2 - The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 μ m, equal pitch, four-level interconnection.

AB - The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 μ m, equal pitch, four-level interconnection.

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SN - 0163-1918

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JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - Proceedings of the 1995 International Electron Devices Meeting, IEDM'95

Y2 - 10 December 1995 through 13 December 1995

ER -

Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

Abstract

ASJC Scopus subject areas

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