TY - JOUR
T1 - GATE-ARRAY LAYOUT SYSTEM
T2 - LOP-ARP2.
AU - Odawara, Gotaro
AU - Tadokoro, Satoshi
AU - Masaki, Hiroshi
AU - Iijima, Kazuhiko
PY - 1984/9
Y1 - 1984/9
N2 - This paper describes a gate-array layout system, LOP-ARP2, as a subsystem of Packaging Automation System (PAS), which is a total design system for digital circuits. A new placement technique is proposed: Hierarchical Force Directed Technique considering Circuit Structure, which has been proved to be efficient to large scale gate-arrays.
AB - This paper describes a gate-array layout system, LOP-ARP2, as a subsystem of Packaging Automation System (PAS), which is a total design system for digital circuits. A new placement technique is proposed: Hierarchical Force Directed Technique considering Circuit Structure, which has been proved to be efficient to large scale gate-arrays.
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M3 - Article
AN - SCOPUS:0021485146
SN - 0563-7937
VL - 37
SP - 921
EP - 932
JO - Journal of the Faculty of Engineering, University of Tokyo, Series B
JF - Journal of the Faculty of Engineering, University of Tokyo, Series B
IS - 4
ER -