Gate structure dependence of variability in polycrystalline silicon fin-channel flash memories

Yongxun Liu, Takahiro Kamei, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'Uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Tetsuro Hayashida, Kunihiro Sakamoto, Atsushi Ogura, Meishoku Masahara

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Polycrystalline silicon (poly-Si) fin-channel tri-gate (TG)- and double-gate (DG)-type flash memories with a thin n+-poly-Si floating gate (FG) and different control-gate (CG) lengths (LCG's) from 76 to 256nm have been fabricated and their electrical characteristics including statistical threshold voltage (Vt) and subthreshold slope (S-slope) have been comparatively investigated before and after one program/erase (P/E) cycle. It was experimentally found that better short-channel effect (SCE) immunity, a smaller Vt variation, and a higher program speed are obtained in TG-type flash memories than in DG-type memories. The higher performance of TG-type flash memories is contributed by the additional top gate and recessed bottom silicon dioxide (SiO2) regions, which strengthen the controllability of the channel potential and increase the coupling ratio of the FG to the CG. Therefore, the developed poly-Si fin-channel TG structure is expected to be very useful for the fabrication of high-density and lowcost flash memories.

Original languageEnglish
Article number06GE01
JournalJapanese Journal of Applied Physics
Issue number6 PART 2
Publication statusPublished - 2013 Jun


Dive into the research topics of 'Gate structure dependence of variability in polycrystalline silicon fin-channel flash memories'. Together they form a unique fingerprint.

Cite this