Hardware implementations of hash function Luffa

Akashi Satoh; Toshihiro Katashita; Takeshi Sugawara; Naofumi Homma; Takafumi Aoki

doi:10.1109/HST.2010.5513102

Hardware implementations of hash function Luffa

Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents hardware architectures for the hash algorithm Luffa, which is a candidate for the next-generation hash standard SHA-3. The architectures were implemented by using a 90-nm CMOS standard cell library. A high throughput of 35 Gbps for a high-speed architecture and a gate count of 14.7 kgate for a compact architecture were obtained. In comparison with Keccak, other SHA-3 candidate in the sponge function category, as well as with the current hash standard SHA-256, Luffa exhibited the advantage of flexible implementation ranging from high-speed to compact circuits.

Original language	English
Title of host publication	Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Pages	130-134
Number of pages	5
DOIs	https://doi.org/10.1109/HST.2010.5513102
Publication status	Published - 2010 Aug 24
Event	2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010 - Anaheim, CA, United States Duration: 2010 Jun 13 → 2010 Jun 14

Publication series

Name	Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010

Other

Other	2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Country/Territory	United States
City	Anaheim, CA
Period	10/6/13 → 10/6/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

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10.1109/HST.2010.5513102

Cite this

Satoh, A., Katashita, T., Sugawara, T., Homma, N., & Aoki, T. (2010). Hardware implementations of hash function Luffa. In Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010 (pp. 130-134). [5513102] (Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010). https://doi.org/10.1109/HST.2010.5513102

Hardware implementations of hash function Luffa. / Satoh, Akashi; Katashita, Toshihiro; Sugawara, Takeshi et al.
Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010. 2010. p. 130-134 5513102 (Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Satoh, A, Katashita, T, Sugawara, T, Homma, N & Aoki, T 2010, Hardware implementations of hash function Luffa. in Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010., 5513102, Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010, pp. 130-134, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010, Anaheim, CA, United States, 10/6/13. https://doi.org/10.1109/HST.2010.5513102

Satoh A, Katashita T, Sugawara T, Homma N , Aoki T. Hardware implementations of hash function Luffa. In Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010. 2010. p. 130-134. 5513102. (Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010). doi: 10.1109/HST.2010.5513102

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Hardware implementations of hash function Luffa

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