High-performance 0.1-μm gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

Tetsuya Suemitsu, Haruki Yokoyama, Yohtaro Umeda, Takatomo Enoki, Yasunobu Ishii

Research output: Contribution to journalArticlepeer-review

50 Citations (Scopus)


Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMT's (E-HEMT's) are described for the first time. Most important issue for the fabrication of E-HEMT's is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 Ω·mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-μm gate E-HEMT's. This is therefore one of the promising devices for ultra-high-speed applications.

Original languageEnglish
Pages (from-to)1074-1080
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number6
Publication statusPublished - 1999


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