High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Y. J. Lee; T. C. Hong; F. K. Hsueh; P. J. Sung; C. Y. Chen; S. S. Chuang; T. C. Cho; S. Noda; Y. C. Tsou; K. H. Kao; C. T. Wu; T. Y. Yu; Y. L. Jian; C. J. Su; Y. M. Huang; W. H. Huang; B. Y. Chen; M. C. Chen; K. P. Huang; J. Y. Li; M. J. Chen; Y. Li; S. Samukawa; W. F. Wu; G. W. Huang; J. M. Shieh; T. Y. Tseng; T. S. Chao; Y. H. Wang; W. K. Yeh

doi:10.1109/IEDM.2016.7838535

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Y. J. Lee, T. C. Hong, F. K. Hsueh, P. J. Sung, C. Y. Chen, S. S. Chuang, T. C. Cho, S. Noda, Y. C. Tsou, K. H. Kao, C. T. Wu, T. Y. Yu, Y. L. Jian, C. J. Su, Y. M. Huang, W. H. Huang, B. Y. Chen, M. C. Chen, K. P. Huang, J. Y. LiM. J. Chen, Y. Li, S. Samukawa, W. F. Wu, G. W. Huang, J. M. Shieh, T. Y. Tseng, T. S. Chao, Y. H. Wang, W. K. Yeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

Original language	English
Title of host publication	2016 IEEE International Electron Devices Meeting, IEDM 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	33.5.1-33.5.4
ISBN (Electronic)	9781509039012
DOIs	https://doi.org/10.1109/IEDM.2016.7838535
Publication status	Published - 2017 Jan 31
Event	62nd IEEE International Electron Devices Meeting, IEDM 2016 - San Francisco, United States Duration: 2016 Dec 3 → 2016 Dec 7

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	62nd IEEE International Electron Devices Meeting, IEDM 2016
Country/Territory	United States
City	San Francisco
Period	16/12/3 → 16/12/7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2016.7838535

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Lee, Y. J., Hong, T. C., Hsueh, F. K., Sung, P. J., Chen, C. Y., Chuang, S. S., Cho, T. C., Noda, S., Tsou, Y. C., Kao, K. H., Wu, C. T., Yu, T. Y., Jian, Y. L., Su, C. J., Huang, Y. M., Huang, W. H., Chen, B. Y., Chen, M. C., Huang, K. P., ... Yeh, W. K. (2017). High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications. In 2016 IEEE International Electron Devices Meeting, IEDM 2016 (pp. 33.5.1-33.5.4). [7838535] (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2016.7838535

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications. / Lee, Y. J.; Hong, T. C.; Hsueh, F. K. et al.
2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 33.5.1-33.5.4 7838535 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, YJ, Hong, TC, Hsueh, FK, Sung, PJ, Chen, CY, Chuang, SS, Cho, TC, Noda, S, Tsou, YC, Kao, KH, Wu, CT, Yu, TY, Jian, YL, Su, CJ, Huang, YM, Huang, WH, Chen, BY, Chen, MC, Huang, KP, Li, JY, Chen, MJ, Li, Y, Samukawa, S, Wu, WF, Huang, GW, Shieh, JM, Tseng, TY, Chao, TS, Wang, YH & Yeh, WK 2017, High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications. in 2016 IEEE International Electron Devices Meeting, IEDM 2016., 7838535, Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 33.5.1-33.5.4, 62nd IEEE International Electron Devices Meeting, IEDM 2016, San Francisco, United States, 16/12/3. https://doi.org/10.1109/IEDM.2016.7838535

Lee YJ, Hong TC, Hsueh FK, Sung PJ, Chen CY, Chuang SS et al. High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications. In 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 33.5.1-33.5.4. 7838535. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2016.7838535

Lee, Y. J. ; Hong, T. C. ; Hsueh, F. K. et al. / High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications. 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 33.5.1-33.5.4 (Technical Digest - International Electron Devices Meeting, IEDM).

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title = "High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications",

abstract = "Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.",

author = "Lee, {Y. J.} and Hong, {T. C.} and Hsueh, {F. K.} and Sung, {P. J.} and Chen, {C. Y.} and Chuang, {S. S.} and Cho, {T. C.} and S. Noda and Tsou, {Y. C.} and Kao, {K. H.} and Wu, {C. T.} and Yu, {T. Y.} and Jian, {Y. L.} and Su, {C. J.} and Huang, {Y. M.} and Huang, {W. H.} and Chen, {B. Y.} and Chen, {M. C.} and Huang, {K. P.} and Li, {J. Y.} and Chen, {M. J.} and Y. Li and S. Samukawa and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Tseng, {T. Y.} and Chao, {T. S.} and Wang, {Y. H.} and Yeh, {W. K.}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 62nd IEEE International Electron Devices Meeting, IEDM 2016 ; Conference date: 03-12-2016 Through 07-12-2016",

year = "2017",

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T1 - High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

AU - Lee, Y. J.

AU - Hong, T. C.

AU - Hsueh, F. K.

AU - Sung, P. J.

AU - Chen, C. Y.

AU - Chuang, S. S.

AU - Cho, T. C.

AU - Noda, S.

AU - Tsou, Y. C.

AU - Kao, K. H.

AU - Wu, C. T.

AU - Yu, T. Y.

AU - Jian, Y. L.

AU - Su, C. J.

AU - Huang, Y. M.

AU - Huang, W. H.

AU - Chen, B. Y.

AU - Chen, M. C.

AU - Huang, K. P.

AU - Li, J. Y.

AU - Chen, M. J.

AU - Li, Y.

AU - Samukawa, S.

AU - Wu, W. F.

AU - Huang, G. W.

AU - Shieh, J. M.

AU - Tseng, T. Y.

AU - Chao, T. S.

AU - Wang, Y. H.

AU - Yeh, W. K.

PY - 2017/1/31

Y1 - 2017/1/31

N2 - Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

AB - Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

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SP - 33.5.1-33.5.4

BT - 2016 IEEE International Electron Devices Meeting, IEDM 2016

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 3 December 2016 through 7 December 2016

ER -

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

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