High-performance hardware architectures for Galois Counter Mode

Akashi Satoh, Takeshi Sugawara, Takafumi Aoki

Research output: Contribution to journalArticlepeer-review

29 Citations (Scopus)


Various high-performance hardware architectures for Galois Counter Mode (GCM) in conjunction with various Advanced Encryption Standard (AES) circuits and multiplier-adders are proposed. A total of 17 GCM-AES circuits were synthesized by using a 130-nm CMOS standard cell library, and the trade-offs between speed and hardware resources were evaluated. Our flexible architectures achieved a wide variety of performances from compact (2.56 Gbps with 34.5 Kgates) to high speed (62.6 Gbps with 979.3 Kgates). All of our architectures support key sizes of 128, 192, and 256 bits, while only one previous approach does. Even with variable-length key support, our architecture also achieved the highest hardware efficiency (defined as throughput per gate) among the designs using the same generation of process technology.

Original languageEnglish
Pages (from-to)917-930
Number of pages14
JournalIEEE Transactions on Computers
Issue number7
Publication statusPublished - 2009


  • AES
  • ASIC
  • GCM
  • High-speed hardware
  • Multiplier
  • S-box
  • VLSI

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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