High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction

Akira Mochizuki; Masatomo Miura; Takahiro Hanyu

doi:10.1109/ISMVL.2007.28

High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu

RIEC - Computing System Platforms Division

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

A new multiple-valued comparator based on active-load dual-rail differential logic is proposed for crosstalk-noise reduction while maintaining the switching speed. The use of dual-rail complementary differential-pair circuits (DPCs) whose outputs are summed up each other by wiring makes the common-mode noise reduced, yet the switching speed enhanced. By using the diode-connected cross-coupled PMOS active loads, the rapid transition behaviors in the DPC is relaxed appropriately, which can also eliminate a spike-shaped input noise. It is demonstrated in 0.18μm CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.

Original language	English
Title of host publication	37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Publisher	IEEE Computer Society
Pages	57-62
Number of pages	6
ISBN (Print)	0769528317, 9780769528311
DOIs	https://doi.org/10.1109/ISMVL.2007.28
Publication status	Published - 2007
Event	37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway Duration: 2007 May 13 → 2007 May 16

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Conference

Conference	37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Country/Territory	Norway
City	Oslo
Period	07/5/13 → 07/5/16

Access to Document

10.1109/ISMVL.2007.28

Cite this

Mochizuki, A., Miura, M., & Hanyu, T. (2007). High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction. In 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 (pp. 57-62). Article 4215980 (Proceedings of The International Symposium on Multiple-Valued Logic). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2007.28

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title = "High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction",

abstract = "A new multiple-valued comparator based on active-load dual-rail differential logic is proposed for crosstalk-noise reduction while maintaining the switching speed. The use of dual-rail complementary differential-pair circuits (DPCs) whose outputs are summed up each other by wiring makes the common-mode noise reduced, yet the switching speed enhanced. By using the diode-connected cross-coupled PMOS active loads, the rapid transition behaviors in the DPC is relaxed appropriately, which can also eliminate a spike-shaped input noise. It is demonstrated in 0.18μm CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.",

author = "Akira Mochizuki and Masatomo Miura and Takahiro Hanyu",

year = "2007",

doi = "10.1109/ISMVL.2007.28",

language = "English",

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series = "Proceedings of The International Symposium on Multiple-Valued Logic",

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booktitle = "37th International Symposium on Multiple-Valued Logic, ISMVL 2007",

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note = "37th International Symposium on Multiple-Valued Logic, ISMVL 2007 ; Conference date: 13-05-2007 Through 16-05-2007",

}

Mochizuki, A, Miura, M & Hanyu, T 2007, High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction. in 37th International Symposium on Multiple-Valued Logic, ISMVL 2007., 4215980, Proceedings of The International Symposium on Multiple-Valued Logic, IEEE Computer Society, pp. 57-62, 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, Oslo, Norway, 07/5/13. https://doi.org/10.1109/ISMVL.2007.28

High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction. / Mochizuki, Akira; Miura, Masatomo; Hanyu, Takahiro.
37th International Symposium on Multiple-Valued Logic, ISMVL 2007. IEEE Computer Society, 2007. p. 57-62 4215980 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A new multiple-valued comparator based on active-load dual-rail differential logic is proposed for crosstalk-noise reduction while maintaining the switching speed. The use of dual-rail complementary differential-pair circuits (DPCs) whose outputs are summed up each other by wiring makes the common-mode noise reduced, yet the switching speed enhanced. By using the diode-connected cross-coupled PMOS active loads, the rapid transition behaviors in the DPC is relaxed appropriately, which can also eliminate a spike-shaped input noise. It is demonstrated in 0.18μm CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.

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Mochizuki A, Miura M, Hanyu T. High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction. In 37th International Symposium on Multiple-Valued Logic, ISMVL 2007. IEEE Computer Society. 2007. p. 57-62. 4215980. (Proceedings of The International Symposium on Multiple-Valued Logic). doi: 10.1109/ISMVL.2007.28

High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction

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